Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-10-23
2003-07-08
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S780000, C257S783000
Reexamination Certificate
active
06590286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to land grid array (LGA) semiconductor devices and, more specifically to an LGA semiconductor device which has been improved to provide greater positioning accuracy in mounting an electrode portion on a mounting substrate and greater bonding reliability with respect to the mounting substrate after the mounting. Further, the present invention relates to a method of mounting such an LGA semiconductor device.
2. Description of the Background Art
FIG. 9
is a cross sectional view of a conventional LGA type semiconductor device, and
FIG. 10
is a bottom view thereof.
Referring to
FIGS. 9 and 10
, a semiconductor device
7
includes a substrate
2
. An external electrode
3
is provided on one surface of substrate
2
, and a sealing portion
1
for sealing a semiconductor element or the like is provided on the other surface of substrate
2
which is formed of a material such as a glass epoxy resin. An electrode interconnection made of copper or the like, is provided on the surface of and inside substrate
2
, forming an electrical and physical connection with the semiconductor element. As can be seen, external electrode
3
is exposed on the other surface of substrate
2
that is opposite sealing portion
1
. External electrode
3
is made of copper or the like which forms an electrical and physical connection with the mounting substrate.
External electrode
3
includes an external electrode pad
4
which is cylindrical in shape and having a smooth surface, and an external electrode interconnection
6
extending from the inside to the outside of substrate
2
via a through hole
5
. External electrodes
3
are arranged on a grid, i.e., in area array on the side of substrate
2
that is opposite sealing portion
1
.
Since external electrodes
3
are arranged on a grid in a plane, the structure has an advantage in manufacturing in that the greater number of electrodes can be provided per unit part area despite small pitches between electrodes.
Now, the operation of the conventional LGA type semiconductor device will be described.
Referring to
FIG. 11
, an operation of mounting semiconductor device
7
onto mounting substrate
8
will be described below. Mounting substrate
8
is formed of a material such as a glass epoxy resin. Although not shown, an electrode interconnection made of copper or the like is formed on the surface of mounting substrate
8
, which forms an electrical and physical connection with respect to semiconductor device
7
. Substrate external electrode
9
is exposed from the surface of mounting substrate
8
and made of copper or the like that forms an electrical and physical connection with respect to semiconductor substrate
7
. Substrate external electrodes
9
are provided on the surface of mounting substrate
8
and arranged in area array being opposite to external electrodes
3
of semiconductor device. A bonding medium
10
of a solder paste or the like is printed and applied onto substrate external electrode
9
by means of printing, dispensing or the like.
The mounting operation of conventional semiconductor device
7
is as follows. Namely, bonding medium
10
is preliminarily printed and applied onto substrate external electrode
9
of mounting substrate
8
. In this state, semiconductor device
7
is mounted onto mounting substrate
8
. Next, external electrode pad
4
of semiconductor device
7
is pressed against bonding medium
10
for bonding. Further, mounting substrate
8
mounted with semiconductor device
7
is made to reflow at a temperature of at least the melting point of bonding medium
10
. Thus, bonding medium
10
melts to electrically and physically connect semiconductor device
7
and mounting substrate
8
.
Having the above described structure, the conventional semiconductor device suffers from the following problem. Referring to
FIG. 11
, in mounting semiconductor device
7
onto mounting substrate
8
, external electrode pad
4
and bonding medium
10
fail to bond firmly due to a variation in supply amount of bonding medium
10
, a variation in mounting height caused by deflection of semiconductor device
7
, and so on. As a result, after reflowing, all or some of external electrode pads
4
fail to bond substrate external electrode
9
.
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned problem. An object of the present invention is to provide a land grid array (LGA) type semiconductor device which has been improved to provide greater positioning accuracy for a mounting substrate and semiconductor device in mounting a substrate.
Another object of the present invention is to provide an LGA type semiconductor device which has been improved to provide greater bonding reliability for a mounting substrate and the mounted semiconductor device.
Another object of the present invention is to provide a method of mounting such an LGA type semiconductor device.
An LGA type semiconductor device according to one aspect of the present invention has external electrodes arranged in area array. The external electrode includes an external electrode pad and an external electrode interconnection extending from the inside to the outside of the substrate via a through hole. The external electrode pad includes a first pad layer formed in a cylinder or rectangular column shape, and a second pad layer provided to cover the surface of the first pad layer and formed in a cone or pyramid shape.
According to one preferred embodiment of the present invention, the second pad layer has a recess in its surface.
According to a more preferred embodiment of the present invention, the recess is a groove formed in a cone or pyramid shape.
According to a more preferred embodiment of the present invention, the substrate further has on its one surface a dummy electrode having a shape different from the above mentioned external electrode pad and not electrically nor physically connected to the external electrode pad.
According to a more preferred embodiment of the present invention, the dummy electrode includes a first layer formed in a cylinder or rectangular column shape, and a second layer provided to cover the surface of the first layer and formed in a cone or pyramid shape.
In a method of mounting an LGA type semiconductor device according to a second aspect of the present invention, first of all, an LGA type semiconductor device is prepared including a substrate which has on its one surface external electrodes arranged in area array. The external electrode includes an external electrode pad and an external electrode interconnection extending from the inside to the outside of the substrate via a through hole. The external electrode pad includes a first pad layer formed in a cylinder or rectangular column shape, and a second pad layer provided to cover the surface of the first pad layer and formed in a cone or pyramid shape. A mounting substrate is prepared having a substrate external electrode and a bonding medium provided to cover the surface of the substrate external electrode. The second pad layer of the LGA type semiconductor device is pressed against the bonding medium of the mounting substrate to bond the LGA type semiconductor device to the mounting substrate. The mounting substrate mounted with the LGA type semiconductor device is annealed at a temperature of at least the melting point of the bonding medium.
According to a preferred embodiment of the present invention, the second pad layer has in its surface a recess.
According to a more preferred embodiment of the present invention, the recess is a groove formed in a cone or pyramid shape.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6175157 (2001-01-01), Morifuji
patent: 6313533 (2001-11-01), Funaya et al.
patent: 6420664 (2002-07-01), Muramatsu et al.
Hashimoto Tomoaki
Kasatani Yasushi
Okada Makio
Leydig , Voit & Mayer, Ltd.
Rose Kiesha
Zarabian Amir
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