Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
1999-12-13
2002-03-12
Ta, Tho D. (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S074000, C439S260000, C439S525000
Reexamination Certificate
active
06354844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to an arrangement for making electrical interconnection of electronic devices and, more particularly, to structural components for the alignment and engagement of electronic packages to interposers or sockets and interposers or sockets to printed circuit boards in the interconnection and assembly of electronic devices.
2. Background and Related Art
Shrinking integrated circuit dimensions and greater functionality have dramatically increased the number of input/output connections to integrated circuit packages while decreasing the dimensions available for making the connections. As the requirement for larger numbers of interconnections between integrated circuit chip packages and the boards or cards to which they are attached drives the size and spacing of the interconnect features of the connection points to smaller and smaller values, the difficulty of accurately aligning these features increases. The trend will continue in the foreseeable future. Certain types of packaging interconnect schemes, such as pin connector designs, will not be able to meet the requirements of this fine pitch input/output regime. One packaging interconnect scheme that will be able to meet the requirements of the fine pitch input/output regime is Land Grid Array (LGA) packaging technology. One key packaging advantage of the Land Grid Array is that the connection features on the package and the board are, quite simply, properly prepared plated pads. To make good electrical connection between package and board, all that is needed between the pads on the package and pads on the board is a compliant, conductive interposer or socket that conforms to variables in smoothness and surface flatness of the integrated circuit package and circuit board. In such schemes, the package is pressed against the card with the interposer between by means of a pressure plate, clamping screws and backing plate. One of the difficulties of the Land Grid Array approach to packaging is effective alignment of the packages to the interposer and the interposer to the circuit board.
Various arrangements have been proposed for aligning electronic packages to circuit boards. For example U.S. Pat. No. 5,738,531 to Beaman, et al., describes a self-aligning, low profile, socket using a dendritic interposer for connecting ball grid array packages. U.S. Pat. No. 5,473,510 discloses a land grid array package/circuit board assembly using alignment posts on the interposer for aligning the integrated package to the interposer and interposer to the board.
One difficulty with these and other known packaging techniques resides in the fact that alignment relies upon registration points, such as the edge of the chip substrate in the electronic package. This in turn is highly dependent on the registration of the I/O pads on the substrate to the edge of the substrate at the time the substrate is cut into what will determine its final size. It is well known that input/output pad-to-edge registration is difficult to maintain, particularly when substrates are cut from large panels or laminates. In addition, subsequent processing, such as firing of ceramic substrates, can sometimes result in significant dimensional changes due to shrinkage.
Another difficulty with known packaging techniques resides in the fact that alignment holes are often required in the chip substrate. To place holes in ceramic substrates accurately requires their formation after sintering, with the location of the holes determined in accordance with some form of registration process. The placement of holes into a sintered substrate is difficult due to its extreme hardness and involves slow and costly processes.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, the high density contact requirements of state-of-the-art high density input/output integrated circuit packages is met by simple, accurate and low cost alignment means. More particularly, new and improved alignment means are employed to align the electronic package to the flexible interposer or socket and the flexible interposer or socket to the circuit board. Alignment components are formed with respect to each of the electronic package, flexible interposer and circuit board parts. In accordance with further teachings of the present invention, precise positioning of these alignment components on the respective parts is achieved by forming the components in registration with selected contact pads of the electronic package and/or circuit board and selected pin locations of the array of pin locations of the flexible interposer. By so doing, alignment of these parts at their respective connection points is precisely achieved without the need of registration using a remote, less accurate point of reference.
In one embodiment, alignment pins are positioned and attached to two contact pads on the electronic package substrate and two alignment holes are formed at corresponding contact pad positions on the circuit board. In addition, two alignment holes are formed at corresponding conductive pin locations or positions in the flexible interposer. The alignment pins pass through the alignment holes in the flexible interposer and into the alignment holes in the circuit board. In another embodiment, positioning elements, in the form of shorter pin-like structures, such as solder balls, or the like, are attached to pads at corresponding positions on both the electronic package and circuit board so as to seat within the alignment holes in the flexible interposer.
Accordingly, it is an object of the present invention to provide an improved electronic package interconnection and alignment arrangement.
It is a further object of the present invention to provide an electronic package utilizing an alignment scheme which provides effective electrical connection in a simple, cost effective manner.
It is yet a further object of the present invention to provide effective alignment of electrical connection points in a Land Grid Array package.
It is another object of the present invention to provide improved alignment means for aligning an electronic package to an interposer or socket and an interposer or socket to a circuit board in Land Grid Array technology.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings wherein like reference numbers represent like parts of the invention.
REFERENCES:
patent: 5364286 (1994-11-01), Matsuoka
patent: 5413489 (1995-05-01), Switky
patent: 5713744 (1998-02-01), Laub
patent: 5772451 (1998-06-01), Dozier, II et al.
patent: 5791914 (1998-08-01), Loranger et al.
patent: 5802699 (1998-09-01), Fjelstad et al.
patent: 5805419 (1998-09-01), Hundt et al.
patent: 5833471 (1998-11-01), Selna
Coico Patrick A.
Fasano Benjamin V.
International Business Machines - Corporation
Jordan John A.
Nguyen Truc T
Pepper Margaret A.
Ta Tho D.
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