Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-06-20
2004-05-25
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S119000, C438S458000, C438S977000, C438S692000
Reexamination Certificate
active
06740567
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for fabricating integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for efficiently fabricating integrated circuit microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication functionality levels have increased and microelectronic fabrication integration levels have increased, so also has the complexity of microelectronic fabrication facilities and microelectronic fabrication processes which are employed for fabricating microelectronic fabrications. Similarly, as a result of enhanced complexity of microelectronic fabrication facilities and microelectronic fabrication processes which are employed for fabricating microelectronic fabrications, there is typically also encountered extended microelectronic fabrication process times when fabricating advanced microelectronic fabrications.
While extended microelectronic fabrication process times are often unavoidable when fabricating advanced microelectronic fabrications, extended microelectronic fabrication process times are nonetheless clearly not desirable in the art of microelectronic fabrication insofar as extended microelectronic fabrication process times often in turn provide for inefficient microelectronic fabrication facility and tooling utilization, which further in turn provides for non-optimal microelectronic fabrication facility return on investment and non-optimal microelectronic fabrication tooling return on investment.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials through which microelectronic fabrications may be more efficiently fabricated within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
Various methods and materials have been disclosed in the art of microelectronic fabrication for efficiently fabricating microelectronic fabrications with desirable properties in the art of microelectronic fabrication.
For example, Leedy, in U.S. Pat. No. 5,946,559, discloses a general method for fabricating, with enhanced process flexibility, various microelectronic structures and microelectronic layers when fabricating microelectronic fabrications. To realize the foregoing object, the method employs fabricating and connecting flexible free standing membranes formed of at least microelectronic dielectric materials and microelectronic semiconductor materials, wherein the flexible free standing membranes have formed therein microelectronic structures and microelectronic layers which are desirable when fabricating microelectronic fabrications.
Desirable in the art of microelectronic fabrication are additional methods and materials through which microelectronic fabrications may be more efficiently fabricated within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for fabricating a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the microelectronic fabrication is fabricated efficiently.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a semiconductor integrated circuit microelectronic fabrication. To practice the method of the present invention, there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the present invention, there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication. Finally, there is then laminated the partially fabricated semiconductor integrated circuit microelectronic fabrication with the second substrate to mate the partially fabricated semiconductor integrated circuit microelectronic fabrication with the dielectric isolated metallization pattern to thus form a laminated completely fabricated semiconductor integrated circuit microelectronic fabrication.
There is provided by the present invention a method for fabricating a microelectronic fabrication, wherein the microelectronic fabrication is fabricated efficiently. The present invention realizes the foregoing object by employing when fabricating a semiconductor integrated circuit microelectronic fabrication a partially fabricated semiconductor integrated circuit microelectronic fabrication formed from a first semiconductor substrate having a minimum of one semiconductor device fabricated thereover, wherein the partially fabricated semiconductor integrated circuit microelectronic fabrication is laminated with a second substrate having formed thereover a dielectric isolated metallization pattern to mate the dielectric isolated metallization pattern with the partially fabricated semiconductor integrated circuit microelectronic fabrication. By employing within the context of the present invention a first semiconductor substrate and a separate second substrate, each partially fabricated with respect to a semiconductor integrated circuit microelectronic fabrication, and laminating the first semiconductor substrate and the second substrate to provide a laminated completely fabricated semiconductor integrated circuit microelectronic fabrication, the laminated completely fabricated semiconductor integrated circuit microelectronic fabrication may be formed with enhanced efficiency since at least two separate portions of the laminated completely fabricated semiconductor integrated circuit microelectronic fabrication may be fabricated in parallel.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials, which although not necessarily common in the art of microelectronic fabrication are nonetheless readily adapted to the art of microelectronic fabrication. Since it is thus a specific ordering of methods and materials which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 5514613 (1996-05-01), Santadrea et al.
patent: 5880010 (1999-03-01), Davidson
patent: 5946559 (1999-08-01), Leedy
patent: 6013534 (2000-01-01), Mountain
patent: 6066808 (2000-05-01), Kresge et al.
patent: 6143117 (2000-11-01), Kelly et al.
patent: 6245677 (2001-06-01), Haq
patent: 6309945 (2001-10-01), Sato et al.
Jang Syun-Ming
Liang Mong-Song
Fourson George
Maldonado Julio J.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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