Laminated multilayer package

Details Laminated multilayer package Laminated multilayer package

2005-02-15

2005-02-15

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C029S879000

Reexamination Certificate

active

06856008

ABSTRACT:
The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.

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Deepak K. Pai, “An Approach to Fabricate High Density, Large-Layer-Count PWB,” presented at the Printed Circuits Expo 2000, Apr. 2-6, 2000, San Diego, California, pp. S09-2-1 to S09-2-4.
Deepak K. Pai, “An Approach to Fabricate High Density, Large-Layer-County PWB,” Design Technical Journal, vol. 2, No. 2, Spring/Summer 2000, pp. 16-18.
Deepak K. Pai, “An Approach to Fabricate High Density, Large-Layer-County PWB,” Surface Mount Technology Association (SMTA) International Proceedings 2001, Sep. 30-Oct. 4, 2001, pp. 569-579.

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