Laminated ferrite chip inductor array

Details Laminated ferrite chip inductor array Laminated ferrite chip inductor array

1999-12-14

2001-06-19

Mai, Anh (Department: 2832)

Inductor devices

Coil or coil turn supports or spacers

Printed circuit-type coil

C336S223000, C336S232000, C336S225000

Reexamination Certificate

active

06249206

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a new laminated ferrite chip inductor array which is structurally improved by controlling migration phenomena of silver (Ag) conductors inevitably occurring in an ultra small array holding therein a plurality of adjacent ferrite chip inductors so as to avoid troubles such as bad conditions like an electric short.
Parts of face-mounted type, for example, a ferrite inductor array have already been known where multiple layers of ferrite sheets printed with U-shaped internal conductor patterns
1
and
2
are piled such that the U-shaped patterns on adjacent ferrite sheets are opposed as faced one another, and channels which are composed by sintering the piled layers of coil shaped structure of the internal conductive printed patterns
1
and
2
made electrically communicating via through holes
3
, pierced in the ferrite sheets are, as shown in
FIG. 2
, arranged in parallel within the interior of a ferrite
4
.
In electronic equipment, tendency of miniaturization has recently been intensive and accompanying therewith parts to be used thereto have also been much demanded to be miniaturized. For example, in chip condensers or chip resistors, the specification of a 1005 shape (length: 1 mm, width: 0.5 mm and height: 0.5 mm) is going to be general, and demands for array mounting a plurality of such elements are increasing.
However, in the chip inductor, complicated figures as the coil shaped internal conductive structure as mentioned above must be formed inside of the ferrite porcelain, and so the miniaturization accompanies various difficulties, and the response to demands has considerably been delayed, comparing with the technical fields of condensers or resistors. Nowadays, inductors of a 1608 shape (length: 1.6 mm, width: 0.8 mm and height: 0.8 mm) and arrays of four circuits built-therein of 3216 shape (length: 3.2 mm, width: 1.6 mm and height: 1.6 mm) have been put in practiced at last.
There have been proposals up to now, with respect to the ferrite chip inductor array, that the arrangement of the internal inductors are devised to provide higher inductance with more miniaturized chip sizes (JP-A-5-326270, JP-A-5-326271 and JPA-5-326272). Other several proposals are for improving interaction between circuits, i.e., crosstalk (JP-A-6-338414, JP-A-7-22243, JP-A-8-250333 and JP-A-8-264320).
However, in case of arrays holding therein four circuits of 2010 shape (length: 2.0 mm, width: 1.0 mm and height: 1.0 mm) or less, there occurs a peculiar problem called as a migration phenomenon of the internal conductors which cannot be solved by the conventional art. The migration phenomenon sometimes occurs in multiple layers of ceramics, and when a DC electric field is impressed between the internal conductors, the conductive metal migrates in response to its electric field strength or depending upon a hot and humid environment, and finally it results in an electric short badness. This phenomenon is remarkable in the case where silver is used as the internal conductor. In the inductor of a single circuit, since electric potential is almost the same in any portions of the conductor, the migration phenomenon does not occur and there is no special problem.
On the other hand, in a case of the array, it is required that no short occurs even when the electric potential difference occurs between circuits, and therefore the migration occurs as an important problem. In regard to the migration phenomenon, in case the chip size is 3216 shape or more as before, it is possible to secure an enough space between electrodes, so that the electric field strength is weak, and the conductive metal does not reach a distance generating the short, but in case of chips of 2010 shape or less, since distances between the adjacent conductors is around 100 &mgr;m, the short badness inevitably occurs.
FIGS. 3A and 3B
are explanatory views showing the arrangement of the channels within the laminated ferrite chip inductor array of the prior four circuits type.
FIG. 3A
is an top view, and
FIG. 3B
is a cross sectional view along A—A line of FIG.
3
A. As is seen, the respective channels
5
are disposed by alternately facing the U-shaped internal conductive patterns
1
and the adjacent U-shaped internal conductive patterns
2
, and these internal conductive patterns are electrically communicated via the through holes
3
, and are held in the ferrite.
The array in this Example is composed with four circuits of such channels, and the internal conductive patterns
1
in the channels are arranged in parallel within the same plan face corresponding to one another, while the internal conductive patterns
2
respectively facing them are arranged in parallel within the same plan face corresponding to one another. Each of the channels
5
disposed in the same direction.
As shown in
FIGS. 3A and 3B
, the conventionally existing arrangement makes the same disposal of the internal conductive patterns in the respective channels, and the chip of 3216 sized type does not cause the short badness due to the migration of the metal conductor, but a miniaturization smaller than 2010 sized type causes frequently the short badness by the migration.
SUMMARY OF THE INVENTION
The invention has been realized to provide a structural improvement where even in case of the minute laminated ferrite chip inductor arrays of 2010 shape or less, any short badness does not occur by the migrations of the internal conductive materials.
Inventors of this patent application made earnest studies on avoidance of the electric short badness accompanied with the miniaturization of the ferrite chip inductor arrays, consequently devised relative positions which are disposed with the respective ferrite chip inductors to be held in the arrays, and found it possible to accomplish the object of the structural improvement by separating distances between respective channels as much as possible, and based on this finding they accomplished the invention.
That is to say, the invention is to offer the laminated ferrite chip inductor array, in which the array is composed in that multiple layers of ferrite sheets printed with U-shaped patterns of internal conductors are piled in such a manner that the U-shaped patterns of the internal conductors on adjacent sheets are opposed as faced one another, and a plurality of channels composed by sintering the piled layers of coil-shaped structure of the internal conductive printed patterns made electrically communicating via through holes pierced in the ferrite sheets are held in ferrite porcelains, characterized in that the internal conductive pattern shapes of the adjacent chip inductors are turned 180 degree one another.


REFERENCES:
patent: 4689594 (1987-08-01), Kawabata et al.
patent: 57-190305 (1982-11-01), None
patent: 4-65807 (1992-03-01), None
patent: 5-326272 (1993-12-01), None
patent: 5-326271 (1993-12-01), None
patent: 5-326270 (1993-12-01), None
patent: 6-338414 (1994-12-01), None
patent: 7-22243 (1995-01-01), None
patent: 8-250333 (1996-09-01), None
patent: 8-264320 (1996-10-01), None

Affiliated with

Also associated with

Rating

Laminated ferrite chip inductor array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Laminated ferrite chip inductor array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Laminated ferrite chip inductor array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2515864