Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-09-05
2002-10-01
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S259000, C174S262000, C174S265000, C361S792000, C428S901000
Reexamination Certificate
active
06459047
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to laminate circuit board structures for use in making multilayer printed circuit boards, and in particular to organic circuit board structures for use in such boards.
BACKGROUND OF THE INVENTION
A conventional technique of forming a laminate circuit board structure includes forming layers of dielectric material and layers of electrically conducting material to provide multiple layers of circuits, dielectrics, and voltage planes.
Conventional multilayer printed circuit boards are typically constructed from glass cloth prepreg and copper. Normally copper clad laminates are circuitized and then “laid up” in a sequential fashion with other circuitized cores and additional sticker prepreg (sticker sheets) to form composites. Once laminated, conventional composite boards are drilled and then plated to form multilayer printed circuit boards.
Composites constructed using 2 signal planes and one power plane (2S1P) building block cores, offer a number of advantages over conventional construction techniques. One of these advantages is a 2S1P building block core that is testable prior to composite lamination. Known methods of making 2S1P cores involve drilling or etching clearance holes in bare sheets of copper, laminating these sheets with uncured conventional prepreg and foil, followed by fully curing the laminated sheets to produce a core that can be circuitized to form signal planes. Regardless of the method used to make the 2S1P cores, these are typically adhered using additional “sticker” sheets placed between the 2S1P cores. These additional “sticker” sheets contribute additional thickness and exacerbate many of the problems associated with additional thickness.
More recently, techniques have been provided that enable a relatively inexpensive photo lithographic technique of forming a composite laminate structure from individual discrete laminate structures into a composite laminate structure. Along these lines see U.S. patent applications Ser. No. 09/203,945 entitled “Two Signal One Power Plane Circuit Board”, now U.S. Pat. No. 6,204,453; Ser. No. 09/203,978 entitled “Multi-Layer Organic Chip Carrier Package”, now U.S. Pat. No. 6,201,194; and Ser. No. 09/204,458 entitled “Composite Laminate Circuit and Method of Forming the Same”, now U.S. Pat. No. 6,175,087, entire disclosures of which are incorporated herein by reference.
Although the structures and methods of these inventions provide significant advances and advantages over current multilayer printed circuit board fabrication methods, there still exists a need for further improvement. 2S1P cores built with glass cloth free materials, such as low loss dielectric polymers and polymer precursors allow very small laser drilled holes to be made. One very important aspect in the fabrication of 2S1P cores using low loss dielectric polymers or polymer precursors is the adhesion of these low loss polymers or polymer precursors to the ground plane or power planes which comprise 2S1P core building blocks. Another very important aspect of using these 2S1P cores to build high density multilayer composite printed circuit boards is the method used to adhere the 2S1P cores, and any other layers which comprise the composite, within a multilayer printed circuit board without “sticker” sheets. It is desirable to have a substrate and a method of making a substrate that has good adhesion of low loss polymer or polymer precursors to the ground planes or power planes which comprise 2S1P building block cores. It is also desirable to have a substrate with low loss dielectrics or polymer precursors and a method of making the substrate without “sticker” sheets that can be used in the fabrication of a multilayer printed circuit board.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to enhance the art of packaging technology.
It is another object of this invention to provide a substrate for use in the manufacture of a multilayer printed circuit board, the substrate having a metal layer, an adhesion promoting layer positioned on the metal layer and a partially cured layer of dielectric material positioned on the adhesion promoting layer.
It is yet another object of the invention to provide a method of making such a substrate having a metal layer, an adhesion promoting layer positioned on the metal layer, and a partially cured layer of dielectric material positioned on the adhesion promoting layer.
Another object is to provide such a structure and method that are both adaptable to mass production, thus assuring lower costs.
According to one aspect of the invention, there is provided a substrate comprising a first metal layer having a first surface including at least one through hole therein defined by at least one side wall extending through the first metal layer, an adhesion promoting layer positioned on the first surface of the first metal layer and on the at least one side wall of the through hole, a layer of at least a partially cured dielectric material positioned on the adhesion promoting layer, and a plurality of conductive circuit lines positioned on a portion of the layer of the at least partially cured dielectric material.
According to another aspect of the invention, there is provided a method of making a substrate comprising providing a first metal layer having a first surface including at least one through hole therein defined by at least one side wall extending through the first metal layer, forming an adhesion promoting layer on the first surface of the first metal layer and on the at least one side wall of the through hole, applying a layer of a dielectric material on the adhesion promoting layer, heating the layer of dielectric material so as to at least partially cure the layer of dielectric material, and positioning a plurality of conductive circuit lines on a portion of the layer of the at least partially cured dielectric material.
According to yet another aspect of the invention, there is provided a method of making a substrate comprising providing a first metal layer having a first surface including at least one through hole therein defined by at least one side wall extending through the first metal layer, forming an adhesion promoting layer on the first surface of the first metal layer and on the at least one side wall of the through hole, applying a layer of a low-loss dielectric polymer or a polymer precursor on the adhesion promoting layer, heating the layer of low-loss dielectric polymer or polymer precursor so as to at least partially cure the layer of low-loss dielectric polymer or polymer precursor, and positioning a plurality of conductive circuit lines on a portion of the layer of the at least partially cured low loss dielectric polymer or polymer precursor.
The above objects, advantages, and features of the present invention will become more readily apparent from the following detailed description of the preferred embodiments as illustrated in the accompanying drawings.
REFERENCES:
patent: 3934335 (1976-01-01), Nelson
patent: RE29784 (1978-09-01), Chadwick et al.
patent: 4303715 (1981-12-01), Chang
patent: 4854038 (1989-08-01), Wiley
patent: 4894271 (1990-01-01), Hani et al.
patent: 4911796 (1990-03-01), Reed
patent: 5055342 (1991-10-01), Markovich et al.
patent: 5137461 (1992-08-01), Bindra et al.
patent: 5208068 (1993-05-01), Davis et al.
patent: 5285017 (1994-02-01), Gardner
patent: 5374788 (1994-12-01), Endoh et al.
patent: 5386088 (1995-01-01), Gardner
patent: 5559369 (1996-09-01), Newman
patent: 5709957 (1998-01-01), Chiang et al.
patent: 5879787 (1999-03-01), Petefish
patent: 5930668 (1999-07-01), Gardner
patent: 6120639 (2000-09-01), Redline et al.
patent: 6175087 (2001-01-01), Keesler et al.
patent: 6201194 (2001-03-01), Lauffer et al.
patent: 6204453 (2001-03-01), Fallon et al.
patent: 6333466 (2001-12-01), Miyaake et al.
patent: 6335076 (2002-01-01), Nakamura et al.
“Multi Layer Substrate with Low Coefficient of Thermal Expansion”, K. Nakamura et al., Sep. 22, 2000, 2000 International Symposium on Microelectronics.
Japp Robert M.
Markovich Voya R.
Papathomas Konstantinos I.
Hogg William N.
Patel I B
LandOfFree
Laminate circuit structure and method of fabricating does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Laminate circuit structure and method of fabricating, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Laminate circuit structure and method of fabricating will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2947386