Fabric (woven – knitted – or nonwoven textile or cloth – etc.) – Coated or impregnated woven – knit – or nonwoven fabric which... – Coating or impregnation is electrical insulation-providing,...
Reexamination Certificate
1998-03-02
2001-03-27
Cole, Elizabeth M. (Department: 1771)
Fabric (woven, knitted, or nonwoven textile or cloth, etc.)
Coated or impregnated woven, knit, or nonwoven fabric which...
Coating or impregnation is electrical insulation-providing,...
C442S176000, C442S180000, C427S389900, C427S389800
Reexamination Certificate
active
06207595
ABSTRACT:
TECHNICAL FIELD
The invention relates to insulative laminate materials for use in electronic packages and more particularly to resin and fiber composites which exhibit a high insulation resistance when subjected to severe moisture, temperature, and pressure conditions.
BACKGROUND OF THE INVENTION
Insulative laminate materials are conventionally prepared by impregnating non-woven or woven fiber fabrics (typically glass) with thermosetting resin compositions such as epoxy or bismaleimide-triazine (BT) resins and then drying the fabric. The dried fabric is cut into sheets, referred to in the printed circuit industry as prepregs which are then laminated to solid or personalized electrically conductive layers (typically copper) in various combinations including other previously laminated structures to form single or multi layer substrates.
Holes or vias having electrically conductive walls filled with electrically conductive materials may be formed in the substrate to provide electrical contact between the conductive layers. Numerous other variations to the art of substrate manufacture are well known. The substrates are used to hold electronic components including semiconductors, passive components other substrates, and miscellaneous components such as connectors, switches, or the like and to provide electrical interconnection between appropriate contacts on these components.
The prepreg must exhibit a large number of properties to be used as a substrate material. U.S. Pat. No. 5,648,171 for example, lists high mechanical and thermal strength, good mechanical and thermal stability, thermal undeformabilty, and good aging resistance as requirements. Also listed are good adhesion to glass and copper, good machining properties (punchability, drillability), a low water uptake and high corrosion resistance.
U.S. Pat. No. 5,376,453 notes that resistance to heat deformation is important because the substrate materials are exposed to high temperatures during processing. For example, printed circuit boards are exposed to a temperature of 270° C. during flow soldering. Also temperatures of over 200° C. can occur locally for brief periods during cutting and drilling. In U.S. Pat. No. 5,565,267 the electrically conductive layer is formed with an electrically conductive ink which for most applications would be cured at 200°-230° C. for 30 seconds to 1 hour. Materials with a high glass transition temperature (T
G
) exhibit favorable characteristics because if this glass transition temperature lies above the mentioned values, then inherent stability is guaranteed and damage such as warping is largely ruled out.
U.S. Pat. No. 5,368,921 mentions that use of fibers which have been surface treated with a silane coupling agent or the like is preferred from the standpoint of water resistance. A silane coupling agent is used in U.S. Pat. No. 5,483,101 between an electrically conductive layer and a layer of resin (benzocyclobutene). U.S. Pat. No. 4,783,345 describes resin materials for the manufacture of prepregs which can be stored.
The use of prepreg materials in the manufacture of chip carriers has become more attractive due to their cost advantage over conventional ceramic materials. Furthermore the electrically conductive layer (usually copper) is more conductive and can be processed more readily to very dense geometries than the paste materials typically applied to ceramic carriers. Chip carriers made with prepregs require many of the same characteristics of the prepregs as other substrates. All of the requirements listed above for substrates made with prepregs have been, at least to some extent, successfully addressed. However, chip carriers usually have an additional requirement for a high insulation resistance when subjected to humidity, temperature, and pressure.
When this insulation resistance requirement is added to the requirements above, no satisfactory combination of these properties has previously been achieved.
As a result, chip carriers made of prepregs must be handled in special moisture tight containers. Once a container is opened such a chip carrier must be soldered to a next level carrier such as a printed circuit board within a relatively short period of time. If such a chip carrier is not used within the time limit it must be slowly baked to remove moisture and again resealed in a moisture tight container. Industry wide specifications have been developed to allow component manufacturers to specify these time limits and handling procedures. Obviously such procedures are a burden to component assemblers because other components, e.g., ceramic, plastic encapsulated, passives, connectors, etc. have no such requirement.
OBJECT OF THE INVENTION
It is therefore an object of the invention to provide a prepreg material which can maintain a high insulation resistance when subjected to moisture, temperature, and pressure stresses.
It is another object to provide such a material for use in chip carrier packages wherein no special handling for moisture susceptibility is needed.
It is a further object to provide such a material in a relatively inexpensive manner particularly adapted to mass production.
It is yet a further object to provide a manner for making such a material which can be accomplished in a facile manner.
These and other objects are attained in accordance with one embodiment of the invention wherein there is provided a fabric material comprising a cloth member having a predetermined maximum thickness and a low percentage by weight of particulates as part thereof, and a hardened resin material substantially encasing the cloth member, including the particulates so that fabric material exhibits a relatively high insulation resistance.
In accordance with another embodiment of the invention there is provided a method of making fabric material exhibiting a high insulation resistance comprising the steps of providing a cloth member having a predetermined maximum thickness and a low percentage by weight of particulates as part thereof, substantially encasing the cloth member, including the particulates with a resin material, and at least partially hardening the resin material.
REFERENCES:
patent: 4579772 (1986-04-01), Bhatt et al.
patent: 4713137 (1987-12-01), Sexton
patent: 4783345 (1988-11-01), Kleeberg et al.
patent: 5368921 (1994-11-01), Ishii et al.
patent: 5376453 (1994-12-01), von Gentzkow et al.
patent: 5483101 (1996-01-01), Shimoto et al.
patent: 5565267 (1996-10-01), Capote et al.
patent: 5648171 (1997-07-01), von Gentzkow et al.
patent: 5670262 (1997-09-01), Dalman
patent: 5677045 (1997-10-01), Nagai et al.
patent: 56-49271 (1981-05-01), None
patent: 7-86710 (1995-03-01), None
patent: 7-97466 (1995-04-01), None
patent: 8-92394 (1996-04-01), None
Listing of Major Subsidiaries and Affiliates of Asahi Company (Printed from the Internet on Aug. 31, 1999).*
JEDEC Standard No. 22-A110, Jul. 1988, “Test Method A110 Highly-Accelerated Temperature and Humidity Stress Test (HAST)”, from JEDEC Council Ballot JCB-88-2, formulated under the cognizance of JC-14-1 Committee on Transportaion/Automotive Electronics.
ANSI/IPC-RB-276, Mar. 1992, “Qualification and performance Specification for Rigid Printed Boards”, American National Standards Institute.
JEDEC Standard No. 22-A112, Apr. 1994, “Moisture-Induced Stress Sensitivity for Plastic Surface Mount Devices”, from JEDEC Council Ballot JCB-94-03, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.
JEDEC Standard No. 22-A113-A, Jun. 1995, “Preconditioning of Plastic Surface Mount Devices Prior to Relibiality Testing”, from JEDEC Council Ballot JCB-95-18, formulated under the cognizance of JC-14.1 Committee on Reliabilty Test Methods for Packaged Devices.
Appelt Bernd K.
Blumberg Lawrence R.
Fotorny William T.
Havens Ross D.
Japp Robert M.
Cole Elizabeth M.
International Business Machines - Corporation
Pivnichny John R.
Singh Arti
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