Multiplex communications – Wide area network – Packet switching
Patent
1991-02-26
1995-11-28
Lee, Thomas C.
Multiplex communications
Wide area network
Packet switching
39520008, 39520015, 39520016, 370 60, 370 54, 36493142, 36494061, 36493103, 3649264, 36493101, 3649314, 36493141, 36493143, 36494206, 36494991, 36494994, 364DIG2, 3642287, 364229, 3642319, 3642388, G06F 1300
Patent
active
054716233
ABSTRACT:
The Lambda network is a single stage, packet-switched interprocessor communication network for a distributed memory, parallel processor computer. Its design arises from the desired network characteristics of minimizing mean and maximum packet transfer time, local routing, expandability, deadlock avoidance, and fault tolerance. The network is based on fixed degree nodes and has mean and maximum packet transfer distances where n is the number of processors. The routing method is detailed, as are methods for expandability, deadlock avoidance, and fault tolerance.
REFERENCES:
patent: 4344134 (1982-08-01), Barnes
patent: 4412281 (1983-10-01), Works
patent: 4445171 (1984-04-01), Neches
patent: 4453630 (1984-06-01), Neches
patent: 4470114 (1984-09-01), Gerhold
patent: 4475192 (1984-10-01), Fernow et al.
patent: 4493021 (1985-01-01), Agrawal et al.
patent: 4593154 (1986-06-01), Takeda et al.
patent: 4630259 (1986-12-01), Larson et al.
patent: 4811210 (1989-03-01), McAulay
patent: 4925311 (1990-05-01), Neches et al.
patent: 4933933 (1990-06-01), Dally et al.
patent: 4943909 (1990-07-01), Huang
patent: 5067124 (1991-11-01), Killat et al.
patent: 5079762 (1992-01-01), Tanabe
patent: 5140584 (1992-08-01), Suzuki
patent: 5157692 (1992-10-01), Horie et al.
patent: 5159595 (1992-10-01), Flanagan et al.
patent: 5175733 (1992-12-01), Nugent
patent: 5181017 (1993-01-01), Frey, Jr. et al.
patent: 5218676 (1993-06-01), Ben-Ayed et al.
patent: 5253248 (1993-10-01), Dravida et al.
Gopal, "Prevention of Store-and-Forward Deadlock in Computer Networks", IEEE Trans. Commun., vol. COM-33, No. 12, Dec. 1985, pp. 1258-1264.
Chan et al, "An Algorithm for Detecting and Resolving Store-and-Forward Deadlocks in Packet-Switched Networks", IEEE Trans. Commun., vol. COM-35, No. 8, Aug. 1987, pp. 801-807.
Gelernter, "A DAG-Based Algorithm for Prevention of Store-and Forward Deadlock in Packet Networks", IEEE Trans. Comput., vol. C-30, No. 10, Oct. 1981, pp. 709-715.
Gunther, "Prevention of Deadlocks in Packet-Switched Data Transport Systems", IEEE Trans. Commun., vol. COM-29, No. 4, Apr. 1981, pp. 512-524.
C. Wu et al., "The Universality of the Shuffle-Exchange Network", IEEE Transactions on Computers, vol. C-30, No. 5, May 1981, pp. 324-332.
H. Siegel et al., "Using the Multistage Cube Network Topology In Parallel Supercomputers", Proceedings of the IEEE, vol. 77, No. 12, pp. 1932-1953, Dec. 1989.
N. Koike et al., "Man-Yo: A Special Purpose Parallel Machine For Logic Design Automation", 1985 International Conference on Parallel Processing, pp. 583-590, Aug. 1985.
V. Balasubramanian et al., "A Fault tolerant Massively Parallel Processing Architecture", Journal of Parallel and Distributed Computing, vol. 4, pp. 363-383, 1987.
F. Wong et al., "A Loop-Structured Switching Network", IEEE Transactions On Computers, vol. C-33, No. 5, pp. 450-455, May 1984.
R. Finkel et al. "The Lens Interconnection Strategy", IEEE Transactions on Computers, vol. C-30, No. 12, pp. 960-965, Dec., 1981.
F. Preparata et al., "The Cube-Connected Cycles: A Versatile Network For Parallel Computation", Communications of the ACM, vol. 24, No. 5 pp. 300-309, May 1981.
Harrity Paul
Lee Thomas C.
LandOfFree
Lambda network having 2.sup.m-1 nodes in each of m stages with e does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lambda network having 2.sup.m-1 nodes in each of m stages with e, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lambda network having 2.sup.m-1 nodes in each of m stages with e will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2020917