Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-07-09
2004-03-23
Jeanglaude, Jean (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S145000, C341S153000, C341S159000
Reexamination Certificate
active
06710730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ladder resistor built into either a successive approximation analog-to-digital converter or ADC or a digital-to-analog converter or DAC used to control a machine system such as a servo-controlled machine.
2. Description of the Prior Art
FIG. 6
is a schematic circuit diagram showing the structure of a prior art ladder resistor as disclosed in Japanese patent application publication (TOKKAIHEI) No. 11-145835.
FIG. 7
is a block diagram showing the structure of a successive approximation ADC having a ladder resistor with 6-bit resolution as shown in FIG.
6
.
In
FIG. 6
, reference numeral
110
denotes a normal resistor group including 64 resistors R
0
A to R
63
A connected in series, and reference numeral
120
denotes a reverse resistor group including the same number of resistors R
0
B to R
63
B connected in series as the plurality of resistors R
0
A to R
63
A included in the normal resistor group
110
, the plurality of resistors R
0
B to R
63
B corresponding to the plurality of resistors R
0
A to R
63
A, respectively. The plurality of resistors R
0
A to R
63
A included in the normal resistor group
110
and the plurality of resistors R
0
B to R
63
B included in the reverse resistor group
120
are formed so that they have the same size. Each of the normal resistor group
110
and the reverse resistor group
120
divides the difference between two fixed voltages VRT and VRB applied thereto from outside the successive approximation ADC or generated in the ADC into 64 (=2
6
) steps. Each of the normal resistor group
110
and the reverse resistor group
120
can thus generate and output 64 reference voltages by way of its 64 taps (i.e., 64 nodes).
In addition, the normal resistor group
110
is divided into four resistor sets each of which contains 16 resistors, as shown in FIG.
6
. These four resistor sets are arranged so that they run in parallel with one another. Similarly, the reverse resistor group
120
is divided into four resistor sets each of which contains 16 resistors, as shown in FIG.
6
. These four resistor sets are arranged so that they run in parallel with one another. Furthermore, the four resistor sets of the reverse resistor group
120
and the four resistor sets of the normal resistor group
110
are alternately aligned in the direction of X of FIG.
6
.
In addition, each resistor included in the normal resistor group
110
and a corresponding resistor included in the reverse resistor group
120
, that is, each resistor pair is arranged so that the two resistors included in each resistor pair are symmetric with respect to the center C of the layout of the ladder resistor. In other words, such the two resistors as R
0
A and R
0
B, R
1
A and R
1
B, . . . , or R
63
A and R
63
B included in each resistor pair are symmetric with respect to the center C of the layout of the ladder resistor.
Furthermore, in
FIG. 6
, reference numeral
130
A denotes a first 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the first resistor set (R
0
A to R
15
A) of the normal resistor group
110
and a plurality of taps of the first resistor set (R
0
B to R
15
B) of the reverse resistor group
120
, and for furnishing a reference voltage which appears at the selected input terminal, reference numeral
130
B denotes a second 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the second resistor set (R
16
A to R
31
A) of the normal resistor group
110
and a plurality of taps of the second resistor set (R
16
B to R
31
B) of the reverse resistor group
120
, and for furnishing a reference voltage which appears at the selected input terminal, reference numeral
130
C denotes a third 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the third resistor set (R
32
A to R
47
A) of the normal resistor group
110
and a plurality of taps of the third resistor set (R
32
B to R
47
B) of the reverse resistor group
120
, and for furnishing a reference voltage which appears at the selected input terminal, reference numeral
130
D denotes a fourth 16-to-1 selector for selecting one input terminal from a plurality of input terminals that are respectively connected to both a plurality of taps of the fourth resistor set (R
48
A to R
63
A) of the normal resistor group
110
and a plurality of taps of the fourth resistor set (R
48
B to R
63
B) of the reverse resistor group
120
, and for furnishing a reference voltage which appears at the selected input terminal, and reference numeral
140
denotes a 4-to-1 selector for selecting one output from the outputs of the first through fourth 16-to-1 selectors
130
A to
130
D. The first through fourth 16-to-1 selectors
130
A to
130
D and the 4-to-1 selector
140
are controlled by a latch/control circuit
700
shown in FIG.
7
.
In
FIG. 7
, reference numeral
300
denotes a sample and holding circuit (abbreviated as S/H from here on) for holding an analog voltage applied thereto by way of an analog input terminal
200
while a 1-bit comparator
600
compares the analog voltage with a threshold voltage, and reference numeral
400
denotes a DAC that is controlled by the latch/control circuit
700
, and that delivers a reference voltage from the ladder resistor
100
or a voltage generated based on the reference voltage to a subtracter
500
as a voltage to be compared. The 1-bit comparator
600
determines whether or not the subtraction result from the subtracter
500
is 0 or more, and then outputs “1” if the subtraction result is 0 or more, and outputs “0” otherwise. The subtracter
500
subtracts the voltage to be compared from the DAC
400
from the analog voltage output from the S/H
300
, and then outputs the subtraction result to the 1-bit comparator
600
. The latch/control circuit
700
latches the output of the 1-bit comparator
600
, and delivers a control signal for determining the voltage to be compared that should be output next by the DAC
400
based on the output of the 1-bit comparator
600
to the DAC
400
, and then furnishes an A/D conversion result to outside the successive approximation ADC by way of an output terminal
800
.
In operation, the ladder resistor
100
divides the difference between two fixed voltages VRT and VRB applied thereto from outside the successive approximation ADC or generated in the ADC into 64(=2
6
) steps. The ladder resistor
100
can thus generate 64 reference voltages, and select one of them and output the selected reference voltage to the DAC
400
. Each of the first through fourth 16-to-1 selectors
130
A to
130
D is controlled by the control signal from the latch/control circuit
700
as shown in FIG.
7
. Each of the first through fourth 16-to-1 selectors selects one reference voltage from 16 reference voltages generated by the corresponding resistor set and outputs the selected reference voltage. The 4-to-1 selector
140
is similarly controlled by the control signal from the latch/control circuit
700
, and selects one reference voltage from four reference voltages selected by the first through fourth 16-to-1 selectors
130
A to
130
D and outputs the selected reference voltage to the DAC
400
. The ladder resistor
100
thus outputs one reference voltage selected by the latch/control circuit
700
to the DAC
400
.
On the other hand, the S/H
300
is holding an analog voltage applied thereto by way of the analog input terminal
200
while the 1-bit comparator
600
compares the analog voltage with a threshold voltage. The DAC is controlled by the latch/control circuit
700
, and delivers a reference voltage from the ladder resistor
100
or a voltage generated based on the reference voltage to the subtracter
500
as a voltage to be compared. The subtracter
500
subtracts the voltage to be compared fr
Harada Hisashi
Miki Takahiro
Burns Doane , Swecker, Mathis LLP
Jeanglaude Jean
Renesas Technology Corp.
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