Ladder gate LDDFET

Details Ladder gate LDDFET Ladder gate LDDFET

1987-07-09

1989-06-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437229, 437233, 437186, 357 233, 156643, H01L 21265

Patent

active

048371807

ABSTRACT:
A method of fabricating a lightly-doped drain field effect transistor (LDDFET) is disclosed. The initial steps include anisotropic polysilicon etching and isotropic photoresist erosion to obtain a ladder-shaped polysilicon gate. The polysilicon is partially oxidized and the source/drain region is formed by the implantation of a heavy dose of n-type ions. Thereafter, the silicon dioxide is removed and a lightly doped source/drain region formed by a second ion implantation between the gate region and the heavily doped source/drain region.

REFERENCES:
Ohta et al., "A Quadruply Self-Aligned MOA (QSA MOS) a New Short Channel High Speed High Density MOSFET for VLSI", IEDM 1979, pp. 581-584.
Huang et al., "A Novel Submicron LDD Transistor with Inverse-T Gate Structure", IEDM 1986, pp. 742-745.

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