Labelling circuit for image processor

Details Labelling circuit for image processor Labelling circuit for image processor

1987-06-29

1989-12-12

Boudreau, Leo H.

Image analysis

Histogram processing

For setting a threshold

382 26, 382 44, G06K 934

Patent

active

048873020

ABSTRACT:
The labelling circuit of this invention comprises first and second table memories, which designate when pixels assigned with different label values are of the same linked components and whose contents are updated based on linked information produced by a label extracting circuit. The labelling circuit further comprises first through third selectors. The first and second selectors select the label value of an intermediate processed image previously produced by the label extracting circuit, or one of label values of new linked information produced by the label extracting circuit, as an address for the first and second table memories. The third selector selects one of output data of the first and second table memories as output image data.

REFERENCES:
patent: 4000399 (1976-12-01), Kawahara
patent: 4069411 (1978-01-01), Morton
patent: 4110737 (1978-08-01), Fahey
patent: 4115805 (1978-09-01), Morton
patent: 4183013 (1980-01-01), Agrawala et al.
patent: 4550434 (1985-10-01), Shimada et al.
patent: 4624013 (1986-09-01), Urushibata
patent: 4718101 (1988-01-01), Ariga et al.

Affiliated with

Also associated with

Rating

Labelling circuit for image processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Labelling circuit for image processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Labelling circuit for image processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2127141