L0 cache alignment circuit

Details L0 cache alignment circuit L0 cache alignment circuit

2006-10-17

2006-10-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S185130, C365S230010

Reexamination Certificate

active

07123496

ABSTRACT:
A L0 cache is provided that includes a plurality of memory cells, full swing signal bit lines coupled to the plurality of memory cells to output full swing data signals, small signal global bit lines coupled to the full swing signal bit lines to provide small signal data signals, and an alignment device to align signals on the small signal global bit lines.

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