Known good die test apparatus and method

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

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324757, G01R 1073

Patent

active

056868421

ABSTRACT:
An apparatus and method for testing an integrated circuit chip prior to mounting on a package including a non-conductive tape upon which are formed a plurality of contacts arranged in a pattern matching the arrangement of bonding pads of an integrated circuit, and a z-axis conductor placed over the conductive tape. The target chip is placed on the z-axis conductor and test signals are transmitted between the contacts on the tape and the bonding pads of the integrated circuit through conductors embedded in the z-axis conductor. In one embodiment, a glass or ceramic plate including openings, arranged in the same pattern as the bonding pads, is placed between the integrated circuit and the z-axis conductor to prevent damage to the integrated circuit.

REFERENCES:
patent: 4783719 (1988-11-01), Jamison et al.
patent: 4922376 (1990-05-01), Pommer et al.
patent: 4955523 (1990-09-01), Calomagno et al.
patent: 5367253 (1994-11-01), Wood et al.

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