Electrical connectors – With coupling movement-actuating means or retaining means in... – Retaining means
Reexamination Certificate
1999-07-14
2002-07-02
Paumen, Gary F. (Department: 2833)
Electrical connectors
With coupling movement-actuating means or retaining means in...
Retaining means
Reexamination Certificate
active
06413113
ABSTRACT:
INTRODUCTION
TECHNICAL FIELD
This invention particularly relates to a cartridge for use in the burn-in and/or test of circuitry formed on semiconductor wafers, before the wafer is diced. The invention may however also be applicable to the burn-in or test of other electrical devices. This invention further relates to methods of loading and aligning a probe card in the cartridge with a semiconductor wafer located in the cartridge. The invention also relates to a connecting device for use in the cartridge. This invention is related to the inventions in commonly owned U.S. Pat. No. 5,429,510, issued to Barraclough et al. on Jul. 5, 1995, entitled “High-Density Interconnect Technique,” and commonly owned U.S. Pat. No. 5,682,472, issued to Brehm et al. on Oct. 28, 1997 and entitled “Method and System for Testing Memory Programming Devices,” the disclosures of which are hereby incorporated by reference herein. This invention is flirther related to the invention in a concurrently filed, copending, commonly owned application entitled “Wafer Level Burn-In and Electrical Test System and Method” (Attorney Docket No. AEHR-007/00US,) the disclosure of which is also incorporated by reference herein.
BACKGROUND OF THE INVENTION
It is well known that integrated circuits (IC's), if they are going to fail, tend to fail early in their projected lives. To identify and eliminate such fragile IC's, IC manufacturers typically expose their integrated circuits to conditions that tend to induce such premature failure. This is known as burn-in, and the typical conditions to which the integrated circuits are exposed during burn-in are elevated temperatures together with the simultaneous application of electrical signals to the integrated circuits. The elevated temperature and the applied signals may exceed normal operating parameters. Once an integrated circuit has passed a test during or after burn-in, the chances of it functioning throughout its intended service life are greatly increased.
Burn-in may be done at various times. In many cases, burn-in is done when the IC is in its final packaged form. In such a case, the IC is plugged into a circuit board that allows the required electrical signals to be applied to the IC. Burn-in of packaged IC's has the advantage that the packaged IC is much less sensitive to physical damage or contamination, and can easily be plugged into the burn-in circuit board to make the required connections. Disadvantages of burning-in packaged IC's are that the added expense of packaging the IC is lost if the IC fails during burn-in, that there are many more individual components to handle, and that the same die type may end up in a number of different package types requiring different fixtures for burn-in.
Another burn-in option is to put individual dies into reusable packages, and then burn-in the die in the reusable package in a similar manner to the burn-in of packaged IC's. This method has the advantage that less has been invested in the IC at this time, but has the disadvantage that the individual dies are difficult to handle conveniently, and are susceptible to damage or contamination.
The cartridge of the invention is used for wafer-level burn-in. That is, the integrated circuit wafer undergoes burn-in before separation into individual dies and traditional packaging. Wafer-level burn-in has the advantages that failure-prone IC's are identified early, that for certain chip types (e.g., DRAM) there is the possibility of laser-repairing burn-in defects, and that wafer maps of burn-in failures are easily generated. Wafer maps assist in identifying and rectifying wafer processing flaws. Wafer-level burn-in has the disadvantages that careful handling of the wafer is required, and that making electrical contact with the wafer is more difficult. An example of a fixture used for wafer-level burn-in is shown in US Pat. No. 5,859,539 to Wood et al.
IC's also typically undergo functional tests at some point. These tests verify that the IC has the required functionality at the desired speed and accuracy. The functional tests can be used to reject IC's entirely, or may be used to classify IC's into different grades.
The cartridge of the invention may be used for wafer-level burn-in and/or testing.
SUMMARY OF THE INVENTION
According to the invention there is provided a method of burning-in or testing a wafer, comprising the steps of placing the wafer on a chuck plate; aligning a probe plate with the wafer; and locking the chuck plate and the probe plate together. Preferably the step of placing the wafer on the chuck plate comprises the step of aligning the wafer with the chuck plate to within a first tolerance and the step of aligning the probe plate with the wafer is done to within a second tolerance, the first tolerance being greater than the second tolerance.
Also according to the invention there is provided a cartridge for wafer-level burn-in or test, comprising a chuck plate to receive a wafer, a probe plate to establish electrical contact with the wafer, and a mechanical connecting device to lock the chuck plate and the probe plate fixed relative to one another. Preferably, the probe plate includes a probe card movably coupled to the probe plate. More preferably, the probe card is mounted to the probe plate by at least two leaf springs and there is a piston slidably located in a recess formed in the probe plate behind the probe card.
Yet further according to the invention there is provided a kinematic coupling comprising a male connector including an undercut surface; and first and second opposed jaws. Each of the jaws is movable from a retracted position in which the male connector can be inserted between the jaws and an engaging position in which the jaws prevent withdrawal of the male connector from between the jaws by engaging the undercut surface of the male connector. Preferably the first and second jaws are biased towards their respective engaging positions, and the first and second jaws each include an inclined surface that can be acted upon by a key to move the first and second jaws into their respective retracted positions. More preferably, the male connector is movably coupled to a substrate such that, when the male connector is inserted between the first and second jaws and the first and second jaws are both in their engaging positions, the male connector is movable relative to the substrate between an extended position in which the engaging surface of the male connector is not in contact with the first and second jaws and a retracted position in which the engaging surface of the male connector is in contact with the first and second jaws. Even more preferably, the male connector is biased towards its retracted position, thereby to provide a positive clamping force.
Still further according to the invention there is provided a wafer level burn-in or test cartridge, comprising:
a first plate;
a second plate;
a male connector that is mounted to the first plate, the male connector including an undercut surface; and
at least one jaw that is movably coupled to the second plate, the jaw being movable from a retracted position in which the male connector can be received by the jaw and an engaging position in which the jaws prevent withdrawal of the male connector from the jaw by engaging the undercut surface of the male connector.
Further details of the invention are set forth in the section entitled: “Description of Specific Embodiments.”
REFERENCES:
patent: 4374317 (1983-02-01), Bradshaw
patent: 5174772 (1992-12-01), Vranish
patent: 5429510 (1995-07-01), Barraclough et al.
patent: 5510724 (1996-04-01), Itoyama et al.
patent: 5568054 (1996-10-01), Iino et al.
patent: 5593903 (1997-01-01), Beckenbaugh et al.
patent: 5597737 (1997-01-01), Greer et al.
patent: 5614837 (1997-03-01), Itoyama et al.
patent: 5682472 (1997-10-01), Brehm et al.
patent: 5743324 (1998-04-01), Kunstreich et al.
patent: 5859539 (1999-01-01), Wood et al.
patent: 5905382 (1999-05-01), Wood et al.
patent: 08204137 (1996-08-01), None
patent: 08222693 (1996-08-0
Andberg John William
Carbone Mark Charles
Richmond, II Donald Paul
Uher Frank Otto
Aehr Test Systems
Gilman Alexander
Paumen Gary F.
Weitz David J.
Wilson Sonsini Goodrich & Rosati
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