Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-08-15
2003-07-29
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S774000, C257S759000, C257S760000, C257S637000, C257S641000, C257S300000, C257S306000, C257S311000, C257S330000, C257S700000, C257S701000
Reexamination Certificate
active
06600228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the top metallization layer of a semiconductor memory device and more particularly to planarization of a passivation layer thereover.
2. Description of Related Art
In the backend process of manufacture of Enhanced Embedded DRAM (EDRAM) devices, we have found the passivation damage at a particular position. After gradually tracing the problem, the SOG gap-filling of passivation layer is the main issue and it causes the worst photoresist profile, therefore, the passivation damage is induced during etching of the passivation layer. We have concluded that the passivation damage results from a pocket or void which causes poor gap-filling above the SOG in the pocket regions. After passivation with a photoresist coating we have found by scanning with a alpha-stepper that the photoresist profile is not as flat and smooth as we anticipated. The poor gap filling is due to the density of metal lines which are formed in an array. The use of a thicker SOG layer did not help.
We have found that passivation damage is not avoidable for mask-sets for 0.35 EDRAM devices, (0.6 &mgr;m/0.6 &mgr;m) by using a current passivation scheme which is as follows:
Form M4—Fourth level Metallization
Form 15,000 Å SiON (PE SiON)
Deposit 3,000 Å SOG (Spin-On-Glass)
Form 10,000 Å SiN (Silicon Nitride)
Using such a process, the SOG layer is absorbed completely by the improper layout pattern (−4000 &mgr;m comb-meander) at the edge of a die. This permits or causes the photoresist to flow into the gap in a succeeding photoresist processing step which involves a soft bake. Thus there is damage during the passivation etch due to poor SOG planarization.
U.S. Pat. No. 4,778,739 of Protschka for “Photoresist Process for Reactive Ion Etching of Metal Patterns for Semiconductor Devices” shows a photoresist rework process for metal lines.
U.S. Pat. No. 5,665,657 of Lee for “Spin-On-Glass Partial Etchback Planarization Process” shows a method for forming a planarization SOG layer which eliminates voids in SOG layers in between closely spaced conductive lines, employing an etch back process.
U.S. Pat. No. 5,567,660 of Chen et al. for “Spin-On-Glass Planarization by a New Stagnant Coating Method” shows a gap fill method to fill gaps between metal lines which method differs from the present invention.
SUMMARY OF THE INVENTION
This invention adds a second photoresist step over a silicon nitride layer over a metallization (e.g., M4) layer.
Passivation damage is avoided everywhere including even a severe top metal rule with a about a 4000 &mgr;m comb-meander for an 8,000 Å metal height.
The result of the process of this invention is gap-filling and more particularly planarization of the passivation layer thereover.
In accordance with this invention, a method is provided for planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device.
The method includes the following steps.
Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap in the silicon nitride layer.
Strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap.
Then, form a blanket, second photoresist layer above the blanket layer.
Preferably, the gap has a neck with a width of from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck, and the partial stripping of the first photoresist layer is performed by an etching process including wet and dry processing.
In accordance with another aspect of the invention, a method is provided for planarizing a surface of a photoresist layer is formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device, comprising the following steps.
Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap.
Strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap, and Form a blanket, second photoresist layer above the blanket layer.
Preferably, in either aspect of the method of this invention, the partial stripping of the first photoresist layer is performed by an etching process. Preferably wet and dry processing is used in the etching process.
In accordance with still another aspect of this invention, a semiconductor device is covered with a blanket silicon nitride layer with a gap therein above a keyhole in metallization of the device. A gap filling first photoresist layer has been formed in the gap above the blanket layer with a damaged surface caused by the gap etched back to leave the first photoresist layer in the gap. A blanket, second photoresist layer is formed above the blanket layer. The first photoresist layer is coated on the silicon nitride and subjected to a soft bake prior to formation of the second photoresist layer which had been formed by coating, soft baking, exposure, developing and a hard baking.
REFERENCES:
patent: 4778739 (1988-10-01), Protschka
patent: 5068711 (1991-11-01), Mise
patent: 5567660 (1996-10-01), Chen et al.
patent: 5665657 (1997-09-01), Lee
patent: 5670384 (1997-09-01), Needham
patent: 6030706 (2000-02-01), Eissa et al.
patent: 6143644 (2000-11-01), Chen et al.
patent: 6207546 (2001-03-01), Chen et al.
patent: 6445072 (2002-09-01), Subramanian et al.
patent: 2002/0175146 (2002-11-01), Dokumaci et al.
Chiang Min-Hsiung
Huang Jenn Ming
Lee Yu-Hua
Ackerman Stephen B.
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Williams Alexander O.
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