Kerf circuit for modeling of BEOL capacitances

Details Kerf circuit for modeling of BEOL capacitances Kerf circuit for modeling of BEOL capacitances

2000-10-06

2003-09-23

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB

Reexamination Certificate

active

06624651

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to the field of semiconductor circuit testing. More specifically, the invention relates to a kerf circuit for modeling of Back End Of Line (BEOL) capacitances.
2. Background Art
In previous semiconductor technologies, much of the delay of circuits was attributed to the delay of the transistors. When simulating circuits in these technologies, it was not necessary to include the intrinsic delay of the metal interconnect because the delay was dominated by the device delay. Because of this, metal interconnect modeling has never been a major modeling priority.
In current and future technologies, however, the transistors are and will be so small that they no longer contribute as much delay to the overall circuit. More of the delay is and will be attributed to the metal interconnects between devices. If these interconnect delays are not included in circuit simulations of current and future technologies, models could underestimate circuit delay by as much as 30%. If the wiring models are incorrect, this can cause timing violations in hardware that are not detectable in simulation.
In order to model the delay from the metal wiring, test circuits must be created to test the actual resistance and capacitance of the wires. Generally, these types of test structures are placed on a semiconductor wafer in the “kerf” area, which is space on a semiconductor wafer in between chips to be used for manufacturing monitoring and modeling. For these types of structures, metal wire resistance is well understood and circuits to test metal resistance exist. Capacitance can also be tested. However, capacitance testing is currently performed through a very laborious process. In this process, a few capacitance structures are placed in the kerf on a semiconductor wafer. Sometime during the manufacturing process, one of the wafers is taken to a laboratory, connected to the proper testing equipment, and the few capacitance structures are manually tested. In this manner, several different structures may be tested for capacitance.
While the latter capacitance testing process is appropriate for a small number of structures, a normal integrated circuit on a semiconductor wafer can contain hundreds or thousands of different capacitive structures. Moreover, this testing process takes quite a bit of time and manpower. Manufacturing processes can periodically change, leading to potentially different capacitances between batches of semiconductor wafers. Even within a batch of semiconductor wafers, there may be differences in the capacitance of structures on the wafers. It is beneficial to be able to test the semiconductor wafers and report the change in capacitance to design engineers and/or process engineers. However, the current testing process is so slow that feedback to the engineers can take a long time. Finally, the current testing process requires a laboratory with particular equipment and procedures, and it is not suitable for testing in a processing line, with its large volumes of semiconductor wafers.
What is needed is a way of testing capacitance for capacitive structures on a semiconductor wafer that overcomes the problems of insufficient numbers of tests performed for capacitive structures, insufficient numbers of capacitance tests performed on wafers, and not being able to perform in-line testing of capacitances.
DISCLOSURE OF INVENTION
To overcome these problems, a kerf circuit for modeling of Back End Of Line (BEOL) capacitances is disclosed. The kerf circuit contains a clock circuit connected to a number of capacitance testing circuits. Each capacitance testing circuit acts a “bay” that can be configured to test one particular capacitance. The clock circuit allows the capacitance testing circuits to charge and discharge the capacitive structures being tested. By having a number of different capacitance testing circuits, capacitances of many different structures may be tested at one time. This is particularly true if the kerf circuit is repeated several or many times, with each different kerf circuit containing different capacitive testing circuits that themselves contain different capacitive structures.
The kerf circuit interfaces to testing equipment through pads. The pads connect to each capacitive testing circuit and allow capacitance measurements to be performed by measuring current. Because the pads are easily connected through probes to testing equipment, many semiconductor wafers can be tested quickly and easily. Many different types of capacitive structures can be tested within a short period of time using already existing equipment.


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