Active solid-state devices (e.g. – transistors – solid-state diode – With shielding
Reexamination Certificate
2001-07-27
2002-07-09
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
With shielding
C257S295000, C257S390000, C438S003000
Reexamination Certificate
active
06417561
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed generally to magnetic memory devices for storing digital information and, more particularly, to methods and structures for confining magnetic fields produced by these devices.
2. Description of the Related Art
The digital memory most commonly used in computers and computer system components is the dynamic random access memory (DRAM), wherein voltage stored in capacitors represents digital bits of information. Electric power must be supplied to these memories to maintain the information because, without frequent refresh cycles, the stored charge in the capacitors dissipates, and the information is lost. Memories that require constant power are known as volatile memories.
Non-volatile memories do not need refresh cycles to preserve their stored information, so they consume less power than volatile memories. There are many applications where non-volatile memories are preferred or required, such as in cell phones or in control systems of automobiles.
Magnetic random access memories (MRAMs) are non-volatile memories. Digital bits of information are stored as alternative directions of magnetization in a magnetic storage element or cell. The storage elements may be simple, thin ferromagnetic films or more complex layered magnetic thin-film structures, such as tunneling magnetoresistance (TMR) or giant magnetoresistance (GMR) elements.
Memory array structures are formed generally of a first set of parallel conductive lines covered by an insulating layer, over which lies a second set of parallel conductive lines, perpendicular to the first lines. Either of these sets of conductive lines can be the bit lines and the other the word lines. In the simplest configuration the magnetic storage cells are sandwiched between the bit lines and the word lines at their intersections. More complicated structures with transistor or diode configurations can also be used. When current flows through a bit line or a word line, it generates a magnetic field around the line. The arrays are designed so that each conductive line supplies only part of the field needed to reverse the magnetization of the storage cells. Switching occurs only at those intersections where both word and bit lines are carrying current. Neither line by itself can switch a bit; only those cells addressed by both bit and word lines can be switched.
Magnetic memory arrays can be fabricated as part of integrated circuits (ICs) using thin film technology. As for any IC device, it is important to use as little space as possible. But as packing density is increased, there are tradeoffs to be considered. When the memory cell size is reduced, the magnetic field required to write to the cell is increased, making it more difficult for the bit to be written. When the width and thickness of bit lines and word lines are reduced, there is higher current density, which can cause electromigration problems in the conductors. Additionally, as conducting lines are made closer together, the possibility of cross talk between a conducting line and a cell adjacent to the addressed cell is increased. If this happens repeatedly, the stored magnetic field of the adjacent cell is eroded through magnetic domain creep, and the information in the cell can be rendered unreadable.
In order to avoid affecting cells adjacent to the ones addressed, the fields associated with the bit and word lines must be strongly localized. Some schemes to localize magnetic fields arising from conducting lines have been taught in the prior art.
In U.S. Pat. No. 5,039,655, Pisharody taught a method of magnetically shielding conductive lines in a thin-film magnetic array memory on three sides with a superconducting film. At or near liquid nitrogen temperatures (i.e., below the superconducting transition temperature), superconducting materials exhibit the Meissner effect, in which perfect conductors cannot be permeated by an applied magnetic field. While this is effective in preventing the magnetic flux of the conductive line from reaching adjacent cells, its usefulness is limited to those applications where very low temperatures can be maintained.
In U.S. Pat. No. 5,956,267, herein referred to as the '267 patent, Hurst et al. taught a method of localizing the magnetic flux of a bottom electrode for a magnetoresistive memory by use of a magnetic keeper. A layered stack comprising barrier layer/soft magnetic material layer/barrier layer was deposited as a partial or full lining along a damascene trench in a insulating layer. Conductive material was deposited over the lining to fill the trench. Excess conductive material and lining layers that were on or extended above the insulating layer were removed by polishing. Thus, the keeper material lined bottom and side surfaces of the bottom conductor, leaving the top surface of the conductor, facing the bit, free of the keeper material.
The process of the '267 patent aids in confining the magnetic field of the cell and avoiding cross-talk among bits. A need exists, however, for further improvements in lowering the writing current for a given magnetic field. By lowering the current required to write to a given cell, reliability of the cell is improved.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a magnetic memory array is provided. The array includes a series of top electrodes in damascene trenches wherein each top electrode is in contact with a top magnetic keeper on at least one outer surface of each top electrode, a series of bottom electrodes arranged perpendicular to the top electrodes and bit regions sensitive to magnetic fields and located between the top electrodes and the bottom electrodes at the intersections of the top electrodes and the bottom electrodes. The bit regions may comprise multi-layer tunneling magnetoresistance (TMR) or giant magnetoresistance (GMR) structures.
In accordance with another aspect of the invention, a magnetic memory device is provided in an integrated circuit. The device comprises a bottom electrode over a semiconductor substrate, a bit region sensitive to magnetic fields over the bottom electrode and an upper electrode in a damascene trench in an insulating layer. The upper electrode has a bottom surface facing toward the bit region, a top surface facing away from the bit region and two side surfaces facing away from the bit region. The device also includes a magnetic keeper in contact with at least one surface of the upper electrode.
In accordance with another aspect of the invention, a magnetic keeper for a top conductor of a magnetic random access memory (MRAM) device is provided. The magnetic keeper comprises a magnetic layer extending along the sidewalls of the top conductor. There is a barrier layer between the magnetic layer and the surrounding insulating layer. The barrier layer also intervenes between a bottom edge of the magnetic layer and the underlying magnetic storage element. In some embodiments, the top conductor is a conductive word line in a damascene trench and is made of copper. The barrier layer may comprise tantalum, and the magnetic layer may comprise cobalt-iron.
In accordance with yet another aspect of the invention, a top conductor is provided in a trench in an insulating layer over a magnetic memory device. As part of the top conductor, a magnetic material lining layer is provided along each sidewall of the trench between the conducting material and the insulating layer. The top surface of the lining layer slopes downward from where it meets the insulating layer to where it meets the conducting material.
In one embodiment, the top conductor also includes a first barrier layer between the magnetic material lining layer and each sidewall of the trench. The top surface of the first barrier layer slopes downward from where it meets the insulating layer to where it meets the magnetic lining layer. In another aspect, the top conductor also includes a second barrier layer between the magnetic material lining layer and the conducting material. The top surface of the sec
Ho Tu-Tu
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Nelms David
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