(k)-Instructions-at-a-time pipelined processor for parallel exec

Details (k)-Instructions-at-a-time pipelined processor for parallel exec (k)-Instructions-at-a-time pipelined processor for parallel exec

1983-03-14

1986-06-10

Thomas, James D.

Boots, shoes, and leggings

364736, 364900, G06F 700, G06F 742

Patent

active

045946558

ABSTRACT:
Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.

REFERENCES:
patent: 3689895 (1972-09-01), Kitamura
patent: 3787673 (1974-01-01), Watson et al.
patent: 3840861 (1974-10-01), Amdahl et al.
patent: 3928857 (1975-12-01), Carter et al.
patent: 3932845 (1976-01-01), Beriot
patent: 3949379 (1976-04-01), Ball
patent: 3969702 (1976-07-01), Tessera
patent: 4057846 (1977-11-01), Cockerill et al.
patent: 4062058 (1977-12-01), Haynes
patent: 4085450 (1978-04-01), Tulpule
patent: 4152763 (1979-05-01), Shimoi
patent: 4365311 (1982-12-01), Fukunoga et al.
"Variable I-Fetch", D. K. Hardin, IBM TDB, vol. 20, No. 7, 12/77, pp. 2547-2548.
"Parallel Pipeline Organization of Execution Unit", D. Sofer and W. W. Sproul, III IBM TDB, vol. 14, No. 10, 03/72, pp. 2930-2933.
"Load Bypass for Address Arithmetic", J. S. Liptay and J. W. Rymarczyk, IBM TDB, vol. 20, No. 9, 02/78, pp. 3606-3607.
"Sequential I-Fetching Mechanisms," J. H. Pomerene et al., IBM TDB, vol. 25, No. 1, Jun. 1982, pp. 124-125.
"Eliminating the Overhead of Floating Point Load and Store Instructions by Decoding Two Instructions Per Cycle in the Floating Point Unit", T. K. M. Agerwala et al., IBM TDB, vol. 25, No. L, Jun. 1982, pp. 126-129.
Irwin, "A Pipelined Processing Unit for On-Line Division," The 5th Annual Symposium on Computer Architecture, Apr. 3-5, 1978, pp. 24-30, 78CH1284-9C 1979, IEEE.
Irwin and Heller, "Online Pipeline Systems for Recursive Numeric Computations", The 7th Annual Symposium on Computer Architecture, May 6-8, 1980, pp. 292-299, CH1494-4/80/0000-0292 1979 IEEE.
Lang et al., "A Modeling Approach and Design Tool for Pipelined Central Processors," The 6th Annual Symposium on Computer Architecture, Apr. 23-25, 1979, pp. 122-129, CH1394-6/79-0000-0122 1979 IEEE.
Owens et al., "On-Line Algorithms for the Design of Pipeline Architectures", The 6th Annual Symposium on Computer Architecture, Apr. 23-25, 1979, pp. 12-19, CH1394-6/79/0000-0012 1979, IEEE.
Patel, "Pipelines with Internal Buffers", The 5th Annual Symposium on Computer Architecture, Apr. 3-5, 1978, pp. 249-254, 78CH1284-9C 1979, IEEE.

Affiliated with

Also associated with

Rating

(k)-Instructions-at-a-time pipelined processor for parallel exec does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with (k)-Instructions-at-a-time pipelined processor for parallel exec, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and (k)-Instructions-at-a-time pipelined processor for parallel exec will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2408405