Patent
1978-06-16
1980-01-22
Wojciechowicz, Edward J.
357 23, 357 52, 357 90, 357 91, H01L 2980
Patent
active
041852915
ABSTRACT:
A junction-type FET comprising a semiconductor substrate 21 of a first conductivity type, and island region 22 of a second conductivity type which comprises a channel region and is selectively formed in the semiconductor substrate 21, and a buried isolating region 27 which is selected from the group consisting of an intrinsic layer, a low impurity concentration layer of the second conductivity type and a layer of first conductivity type, the buried isolating layer being formed by ion implantation of impurities of the first conductivity type in the island region 22 while keeping the impurity concentration at the surface thereof relatively high, and the buried isolating layer substantially isolating the channel region from the surface.
REFERENCES:
patent: 3656031 (1972-04-01), Breese et al.
patent: 3936857 (1976-02-01), Ota
patent: 4053915 (1977-10-01), Cave
Hirao Takashi
Inoue Kaoru
Onuma Takeshi
Sugawa Toshio
Takayanagi Shigetoshi
Matsushita Electric - Industrial Co., Ltd.
Wojciechowicz Edward J.
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