Junction programmable vertical transistor with high performance

Details Junction programmable vertical transistor with high performance Junction programmable vertical transistor with high performance

1988-10-07

1990-10-02

Carroll, J.

357 13, 357 34, 357 91, H01L 2990, H01L 2972, H01L 2702

Patent

active

049611020

ABSTRACT:
An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by eliminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacture PROMs from vertical NPN transistors. An LV.sub.CEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allowing junction avalanching of selected emitter-base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.

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