Junction isolation

Details Junction isolation Junction isolation

2000-06-28

2002-03-05

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S240000, C438S396000

Reexamination Certificate

active

06352903

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is integrated circuit processing, in particular low-capacitance high speed circuits.
BACKGROUND OF THE INVENTION
It is well known in the field that junction capacitance between sources and drains (S/D) and the substrate is an important limiting factor in circuit performance. In addition, S/D to substrate leakage results in useless power consumption. Furthermore, contacts to SID diffusions may suffer form reliability concerns if the etch of the contacts places the conductive material of the contact in close proximity to the bottom junction edge through overetch or misalignment.
Silicon on insulator technology has less junction capacitance than bulk technology because the buried insulator reduces the capacitance, but is more expensive.
It is desirable to develop a low-capacitance transistor structure with low SID leakage for bulk silicon integrated circuits that is economical to manufacture.
SUMMARY OF THE INVENTION
A feature of the invention is the formation of conductive contact pads over a portion of the STI to reduce the area, reduce capacitance and leakage between the source/drain and the silicon substrate.
Another feature of the invention is a reduced size of the transistor area within the shallow trench isolation (STI) that is less than would have been required to provide space for contacts to the rest of the circuit if these contacts were fully within the active region.


REFERENCES:
patent: 5316982 (1994-05-01), Matsuo et al.
patent: 5976928 (1999-11-01), Kirin et al.
patent: 6030867 (2000-02-01), Chien et al.
patent: 6184078 (2001-02-01), Yoon et al.
patent: 6200854 (2001-04-01), Chuang
patent: 6235575 (2001-05-01), Kasai et al.
patent: 2000195967 (2000-07-01), None

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