Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-08-16
2001-08-07
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S286000, C257S328000, C257S329000, C257S330000, C257S256000, C257S263000, C438S186000, C438S192000
Reexamination Certificate
active
06271550
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a JFET transistor whose pinch-off voltage can be set by layout measures.
Depending on the specific requirements to be fulfilled by a transistor, a JFET transistor may be preferable to a MOS transistors. Thus, for instance, a JFET transistor has a lower noise than a MOS transistor because the current flow through a JFET transistor is not caused by surface effects but occurs “in the depth” below the surface of the substrate.
The state of the art includes JFET transistors configured according to
FIGS. 1-3
and produced in CMOS technology. A p-substrate
1
having a surface
2
is provided, by way of diffusion, with an n-well
3
therein which in turn has a p-well
4
embedded therein. Arranged in this p-well
4
are source and drain electrode regions
5
,
6
with a degenerate p-doping, having arranged therebetween a gate electrode region
7
with a degenerate n-doping. As evident from the systematic view of
FIG. 3
, the gate electrode region
7
extends in the manner of a web transversely across the p-well
4
and into the n-well
3
in which the gate electrode region is formed as an annular region
8
surrounding the p-well
4
. The adjacent region of the surface
2
of the p-substrate
1
arranged external of this annular region
8
is covered by field oxide
9
.
In the example of a known JFET transistor illustrated in
FIGS. 1-3
, the p-well
4
forms the channel of the JFET transistor (p-channel JFET transistor). The control of the channel and thus the control of the current flow takes place via the space-charge zone between the gate electrode region
7
and the p-well
4
which in comparison with this electrode region has a considerably weaker doping. As a result of the selected doping material concentrations, this space-charge zone is generated for the most part in the p-well
4
.
By the above configuration, it is accomplished that
the transistor is insulated from the p-substrate by two p-n-transitions, and the substrate potential will thus have no effects on the transistor parameters and particularly on the pinch-off voltage, and
the JFET transistor has a lower noise because of the channel extending below the silicon surface.
The above advantages require suitable wells
3
,
4
, wherein the n-well
3
must be significantly deeper than the p-well
4
to obtain the necessary insulating characteristics and voltage sustaining capabilities. For setting the desired pinch-off voltage, there are required, on the one hand, an exactly defined depth of the gate electrode region
7
and, on the other hand, an exact depth of the p-well
4
as well as an exactly set doping material concentration in the p-well
4
.
An integration of the known construction into an existing CMOS process requires a considerable process expenditure, notably for the following reasons:
In an existing n-well CMOS-process, it becomes necessary to introduce an additional p-well along with a complete change of the beginning of the process (well diffusion/field oxidation/temperature balance).
When using epitaxial substrates, the penetration depth of the n-well is limited by the outdiffusion of the substrate doping.
In a diffused p-well, the surface concentration (voltage sustaining capability of the gate electrode) and the doping profile in the depth (conductivity of the channel) are coupled with each other.
The diffusion depth of the gate electrode is to be exactly adapted to the desired pinch-off voltage and must be controlled.
The pinch-off voltage of the transistor is fixedly determined by the diffusion depths and profiles set in the process.
An adaptation of the well doping/diffusions will at the same time have an influence on nearly all other constructional components.
As evident from the above, it is only by changing the process parameters (diffusion depth of the gate electrode region and depth of p-well
4
) that the pinch-off voltage JFET transistor can be influenced. In an existing CMOS process, however, it is highly undesirable to change the process parameters of individual process steps for individual components.
Thus, it is an object of the invention to provide a JFET transistor which can be produced in CMOS technology without the need to change the process parameters for setting the pinch-off voltage.
SUMMARY OF THE INVENTION
For solving the above object, the instant invention provides a JFET transistor comprising
a semiconductive substrate,
a channel well region of a first conductive type formed in the substrate,
a source and a drain electrode region of the first conductive type which are arranged in a mutually spaced relationship in the channel well region,
a gate electrode region of a second conductive type opposite to the first conductive type, extending between the source and drain electrode regions through the channel well region into the region of the substrate surface external of the channel well region, wherein said region and the rest of the surrounding region of the substrate laterally of and below the channel well region is doped with charge carriers of the second conductive type, and wherein, below the gate electrode region, a channel region is formed within the channel well region, with the cross section of said channel region being controllable by means of space-charge zones formed in the transition regions between the gate electrode region and the channel well region.
According to the instant invention, the above JFET transistor is characterized in that
below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.
In the JFET transistor according to the instant invention, the channel is controlled not only in a vertical direction, as in the state of the art, but also in a lateral direction. For this purpose, the gate electrode region in the channel well region forming the channels has arranged therebelow a plurality of partial regions arranged transversely to the direction of the current flowing between the drain and the source and in a mutually spaced relationship. These partial regions extend from the gate electrode region in a vertical direction through the channel well region into that region in the substrate which is arranged adjacent this channel well region from below. The doping of these partial regions is opposite to the doping of the channel well region but considerably higher than the doping of the channel well region so that space-charge zones are formed laterally between adjacent partial regions in the channel well region. These space-charge zones whose extension depends on the potential of the gate electrode region, change the width of the effective channel, thus allowing a controlling of the current flow and particularly the pinch-off voltage. The pinch-off voltage will thus depend on the distance of the individual partial regions and can be influenced by design and layout measures when developing the JFET transistor. Therefore, the introduction of the inventive laterally effective pinch-off of a channel of a JFET transistor does not require any alterations of the thermal balance or further process steps of the CMOS process used for the manufacture of the JFET transistor so that the manufacturing process for the inventive JFET transistor is CMOS-compatible and is distinguished by a modular process option, i.e. the lateral pinch-off. Suitably, the channel well region is embedded in a further well region, the embedment well region. These two well regions are doped with charge carriers of different conductive types; thus, for instance, the embedment well region has a doping of the n-type while the channel well region has a doping of the p-type.
Particularly suited for the above well-in-well configuration is the thermally induced n-well diffusion as an embedment wel
Birch & Stewart Kolasch & Birch, LLP
Elmos Semiconductor AG
Flynn Nathan
Quinto Kevin
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