Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1995-06-02
2001-03-13
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
Reexamination Certificate
active
06201269
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a junction field effect transistor formed on a semi-insulative compound semiconductor substrate, and also to a method of producing such a transistor.
2. Description of Related Art
Remarkable development is currently in progress with regard to an integrated circuit which is formed on a semi-insulative compound semiconductor substrate composed of GaAs and is adapted for high-speed operation in a gigahertz band of microwave or millimetric wave region. Furthermore, it is presently observed that such integrated circuits are beginning to be employed as an amplifier circuit for a portable telephone or the like using a frequency band of 1 GHz or so. This integrated circuit usually consists of MES field effect transistors or junction field effect transistors.
A conventional n-type junction field effect transistor formed on a semi-insulative compound semiconductor substrate is shown in FIG.
1
.
FIG. 1A
is a typical plan view, and
FIGS. 1B and 1C
are typical partially sectional views taken along lines B—B and C—C in
FIG. 1A
, respectively. It is to be understood that, in some cases hereinafter, such a semi-insulative compound semiconductor substrate will be referred to simply as a substrate, and an ordinary n-type junction field effect transistor will be referred to simply as a field effect transistor in the following description.
An explanation will be given on the summary of a method for production of a conventional n-type junction field effect transistor according to the related art. Although a gate electrode and a source-drain electrode are formed in the field effect transistor, these electrodes are omitted in the diagrams. Further in a diode and a resistance element, there are formed electrodes and terminals as well. However, these are also omitted in the diagrams.
First a source-drain
12
composed of an n
++
-type conductive region is formed by implanting silicon ions into a substrate
10
of GaAs where a photo mask is formed. Thereafter a channel
11
composed of an n
+
-type conductive region is formed by removing the above photo mask, then forming another photo mask, and implanting silicon ions again into the substrate
10
. Subsequently, annealing is executed to activate the ion-implanted silicon which is an n-type impurity.
Next, an insulating film of, e.g., SiN (silicon nitride) is formed by CVD or the like on the entire surface including the channel
11
and the source-drain
12
, and then an opening is formed in the insulating film above the channel
11
by the techniques of photolithography and etching. Thereafter a gate
13
composed of a p
++
-type conductive region is formed by diffusing zinc into the channel
11
through a heating process while causing a gas, which includes diethyl zinc (DEZ), to flow into the opening formed in the insulating film. In this step, the gate
13
is so formed as to protrude outward beyond the channel
11
. More specifically, there is formed a gate extension
13
A which protrudes beyond the channel
11
transversely thereto. When the width of the gate
13
is changed with respect to the channel
11
, a current flowing in the field effect transistor is also changed. Accordingly, in order to attain a sufficient margin in the process of producing a field effect transistor, the structure thereof is so contrived that the gate
13
protrudes outward beyond the channel
11
.
Subsequently an element isolating region
20
is formed for the purpose of ensuring a required electric insulation between mutually adjacent field effect transistors. The element isolating region
20
is formed by implanting boron ions into a substrate region where any field effect transistor is not existent, hence obtaining the structure of FIG.
1
.
In the method of producing such a conventional n-type junction field effect transistor, when boron ions are implanted at the above processing step, the element isolating region
20
is spaced apart by 0.3 &mgr;m to 1.0 &mgr;m from the channel
11
and the source-drain
12
, as shown in
FIGS. 1A
,
1
B and
1
C. Reference numeral
21
denotes a region formed between the element isolating region
20
and both of the channel
11
and the source-drain
12
. A portion
13
B of the gate extension
13
A of the gate
13
protruding outward beyond the channel
11
is in a state not overlapping the element isolating region
20
. The distance from the channel
11
to the element isolating region
20
is dependent solely on the positioning precision of the photo mask at the time of forming the element isolating region
20
by ion implantation.
Due to the existence of such portion
13
B of the gate extension
13
A, there arises a problem that one field effect transistor is adversely affected by another field effect transistor adjacent thereto. More specifically, as shown in a typical partially sectional view of
FIG. 2
, when a positive voltage is applied to a gate
13
of an adjacent field effect transistor while a negative voltage is applied to a source-drain
12
of one field effect transistor, a nonnegligible current comes to flow between one field effect transistor and the adjacent transistor. Hereinafter this current will be referred to as a leakage current. Such a phenomenon is usually termed side-gate effect or back-gate effect. Concretely, a leakage current flows from a portion
13
B of the gate extension
13
A of the adjacent field effect transistor via the region
21
and an area under the element isolating region
20
to the source-drain
12
of one field effect transistor. In
FIG. 6
, a dotted line represents exemplary current-to-voltage characteristic between the source-drain
12
of one field effect transistor and the gate
13
of the adjacent field effect transistor in an example where the element isolating region
20
is spaced apart by 0.3 &mgr;m from the channel
11
(i.e., where the region
21
has a width of 0.3 &mgr;m). In
FIG. 6
, the ordinate signifies the current I (unit: nanoampere) flowing between the source-drain
12
of one field effect transistor and the gate
13
of the adjacent field effect transistor; while the abscissa signifies the voltage difference V (unit: volt) obtained by subtracting the voltage, which is applied to the source-drain
12
of the adjacent field effect transistor, from the voltage applied to the gate
13
of one field effect transistor.
Thus, when a leakage current flows between one field effect transistor and the adjacent field effect transistor, the performance characteristics thereof are adversely affected. It is therefore necessary to minimize such leakage current.
In case a diode is existent adjacently to a field effect transistor, a leakage current flows from a portion
13
B of a gate extension
13
A of the field effect transistor via a region
21
and an area under an element isolating region
20
to an n-type conductive region
23
of the adjacent diode (as shown in a typical diagram of FIG.
3
A). Denoted by reference numeral
24
in
FIG. 3A
is a p-type conductive region.
In another case where a resistance element composed of an n-type conductive region
25
is existent adjacently to a field effect transistor, a leakage current flows from a portion
13
B of a gate extension
13
A of the field transistor via a region
21
and an area under an element isolating region
20
to an n-type conductive region
25
of the adjacent resistance element (as shown in a typical diagram of FIG.
3
B). Generation of such leakage current is not desired either in view of the operation stability of the junction field effect transistor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a junction field effect transistor formed on a semi-insulative compound semiconductor substrate, and also a method of producing such a transistor wherein generation of a leakage current and side-gate effect can be suppressed with a further advantage that harmful influence from any adjacent junction field effect transistor, diode or resistance element is minimized.
In a j
Kawasaki Hidetoshi
Takano Chiaki
Wada Masaru
Kananen Ronald P.
Meier Stephen D.
Rader Fishman & Grauer
Sony Corporation
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