Junction field-effect transistor

Details Junction field-effect transistor Junction field-effect transistor

2002-10-04

2004-05-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C307S402000

Reexamination Certificate

active

06740907

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to junction a field-effect transistor and, more particularly, to a junction field-effect transistor having a gate-source connection in which drain-source leak current I
dss
is decreased, thereby improving FET performance in such factors as gain.
BACKGROUND OF THE INVENTION
The junction FET is formed with a p
+
-type gate region
23
diffused on an n
−
-type semiconductor layer
22
epitaxially grown, for example, on a p
+
-type semiconductor substrate
21
, and an p
−
-type drain region
24
and source region
25
diffused on both sides thereof, as shown in the cross sectional explanatory view FIG.
5
A. It is noted that the semiconductor substrate
21
is connected to the gate electrode
26
and not-shown p
+
-type diffusion region (channel stop) through an interconnection to have, on a back surface thereof, a gate electrode
26
a
for connection onto a die pad. In
FIG. 5A
,
26
is a gate electrode,
27
a drain electrode,
28
a source electrode and
30
an insulating film on a surface of the semiconductor layer
2
.
In this structure, the current between the drain and the source is controlled and amplified depending upon a magnitude of the voltage applied to the gate region
23
. It is known that, the amplification characteristic of this transistor has a close bearing on the drain-source leak current I
dss
that arises when a voltage V between the drain D and the source S is applied in the case that the gate G and the source S are connected together, as shown in FIG.
5
B.
In the junction FET of this kind, the drain-source leak current I
dss
is preferably small and low in variation in order that an FET having a high, stable gain may be obtained, as noted before. However, the current A flowing near a surface of the semiconductor layer
22
and the current B flowing within the semiconductor layer
22
have current variations caused due to the presence of an impurity concentration gradient in the diffusion region, such as the drain region
24
, and semiconductor layer
22
(diffusion region with high impurity concentration particularly nearby the surface). There tends to be great variation among particular manufacture lots. This results in a problem that there is gain decrease or variation in characteristics depending upon the manufacture lot, thus making it impossible to obtain a junction FET having a high gain with stable characteristics. Note that a spread of the depletion layer is shown at C in FIG.
5
A.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve the foregoing problem, and it is an object thereof to provide a high-gain junction field-effect transistor which has low variation in characteristics by reducing the junction-FET drain-source leak current I
dss
to a small, stable value.
A junction field-effect transistor of the invention is a junction field-effect transistor comprising a gate region in a second conductivity type provided on a surface of a first conductivity type semiconductor layer, drain and source regions of a first conductivity type provided sandwiching the gate region on the surface of the first conductivity type semiconductor layer, a gate electrode, a drain electrode and a source electrode respectively connected to the gate region, the drain region and the source region, wherein a diffusion region of the second conductivity type is formed on the surface of the first conductivity type semiconductor layer at least on the region at the side of the drain region close to the gate region in order to be connected to the drain electrode or in a region between the drain and gate regions not connected to the drain electrode.
This structure forms a diffusion region having a conductivity type different from the drain and source regions at the side of the drain region close to the gate region in a semiconductor layer surface where impurity concentration variation tends to occur and leak current readily flows, thus operating as an FLR (field limiting ring). A depletion layer is thus formed at the surface of the epitaxially grown semiconductor layer of the drain and source regions along with the gate region, there by preventing current flow. Thus almost no leak current flows near the surface of the semiconductor layer. As a result, the leak current I
dss
between the drain and the source, where the gate and the source are connected, can be suppressed to a stable, small value. This brings about a stable gain and greatly improves the performance of the FET.


REFERENCES:
patent: 4095252 (1978-06-01), Ochi
patent: 4654548 (1987-03-01), Tanizawa et al.

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