Junction field effect transistor

Details Junction field effect transistor Junction field effect transistor

1978-04-19

1980-07-29

Wojciechowicz, Edward J.

357 20, H01L 2980

Patent

active

042153565

ABSTRACT:
An N.sup.- semiconductor layer is epitaxially grown on an N.sup.+ semiconductor substrate serving as a drain region and overlaid with an N type epitaxial layer. Two opposite P.sup.+ gate regions are disposed in the surface portion of the N layer to define a channel region between them, and an N.sup.+ source region is located above the channel region. That portion of the N layer located between each gate region and the N.sup.- layer has a thickness not smaller than one-half of the channel width of the channel region.

REFERENCES:
patent: 4041517 (1977-08-01), Fuse et al.
Ozawa et al--Jap. Jour. App. Physics--vol. 15, 1976, pp. 171-177.
Nishizawa et al.--IEEE Trans. on Elec. Devices, vol. ED22, No. 4 (1975), pp. 185-197.

Affiliated with

Also associated with

Rating

Junction field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Junction field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Junction field effect transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-907098