JTAG instruction error detection

Details JTAG instruction error detection JTAG instruction error detection

1991-11-27

1994-12-27

Beausoliel, Jr., Robert W.

Excavating

H04B 1700

Patent

active

053771982

ABSTRACT:
A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry. The least significant bit positions of the header and the padding bits are shifted out of the data register prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry such that the least significant bit of the data register is a 1, if no single error occurred, and is a 0 if a single error occurred.

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IEEE Standard Test Access Port and Borndary-Scan Architecture, IEEE Std 1149.1-1990, May 21, 1990.
The Wall Street Journal, Sep. 19, 1990 Edition, Advertisement, pp. A16-A17.

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