Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2002-10-23
2004-06-15
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S772000, C257S773000, C257S780000
Reexamination Certificate
active
06750539
ABSTRACT:
BACKGROUND OF THE INVENTION
Microelectronic elements such as packaged or bare semiconductor chips, discrete components and other elements are mounted to components such as rigid or flexible circuit panels by many different processes. For example, in a so-called “flip chip” or “C4” technique, a bare semiconductive chip is mounted to a circuit panel by disposing solder balls onto contact pads of the chip or circuit panel. The chip is then mounted with its front or contact-bearing surface facing downwardly, toward the first surface of the circuit panel and with the contact pads of the chip aligned with the contact pads of the circuit panel. The assembly is then heated to melt or “reflow” the solder whereupon the assembly is cooled leaving solid solder masses connecting each contact pad of the chip with the corresponding contact pad on the circuit panel.
As described, for example, in Multi-Chip Module Technologies and Alternatives; the Basics (Doame and Franzon, eds., 1993, pp. 450-476), considerable effort has been devoted in the art to development of the flip chip technique. Nonetheless, the flip chip technique typically requires large solder balls to provide solder joints having the strength and fatigue resistance needed to accommodate differential expansion and contraction of the chip and the circuit panel caused by temperature changes during service and/or manufacture. Thus, the flip chip technique typically requires contact pads having large center to center spacings or “pitch.” For these and other reasons, use of the flip chip technique has been limited.
As described, for example, in certain embodiments of commonly assigned U.S. Pat. Nos. 5,148,265, 5,148,266 and 5,915,752, the disclosures of which are hereby incorporated by reference herein, microelectronic components such as semiconductor chips may be connected to components referred to as “interposers” such as flexible dielectric elements having terminals thereon. These connections desirably are made so that the terminals on the connection components remain movable with respect to the chip. A layer of a compliant material as for example, a gel or an elastomer may be provided between the interposer and the microelectronic element. These terminals can then be bonded to contact pads of a larger substrate such as a larger circuit panel. Because the terminals of the interposer remain movable with respect to the chip differential expansion in use does not impose substantial stresses on the connections between the terminals and the substrate.
As described in certain preferred embodiments of U.S. Pat. No. 5,518,964, the disclosure of which is hereby incorporated by reference herein, numerous connections can be made between a microelectronic element and a component such as an interposer by providing leads on the connection component so that one end of each lead is permanently attached to the component whereas another end is releasably attached; juxtaposing the component with a microelectronic element such as a chip or wafer and bonding the tip ends of the leads to the contacts on the microelectronic element. The microelectronic element and interposer are then moved away from one another, typically through a predetermined distance, so as to deform the lead towards vertically extensive disposition. In certain other embodiments taught in the '964 patent, the leads are provided on the microelectronic element rather than on the interposer.
In many of the processes disclosed in the aforesaid patents, an encapsulant is injected around the leads. For example, as taught in certain embodiments of the '964 patent, such an encapsulant may be injected between the interposer and the microelectronic element during or after the movement step so as to form a compliant layer there between surrounding the leads. As described, for example, in commonly assigned U.S. Pat. Nos. 5,706,174 and 5,659,952, the disclosures of which are also incorporated by referent herein, a compliant layer may be formed by providing a porous resilient layer such as a set of compliant standoffs between the connection component and the microelectronic element and connecting the contact pads of the microelectronic element to leads or other conductive features on the connection component. Typically after these connections have been made, a flowable material such as a curable encapsulant is introduced into the porous layer as, for example, between the compliant standoffs and cured so that the flowable material and the original porous layer form a composite complaint layer. The flowable material desirably also encapsulates the electrical connections.
U.S. Pat. No. 5,798,286, the disclosure of which is also incorporated by reference herein describes, in certain embodiments, techniques wherein a plurality of individual semiconductor chips or other separately formed microelectronic elements are assembled to a single connection component or interposer, as, for example, a dielectric sheet having leads thereon with releasable tip ends as discussed above with respect to the '964 patent. In certain disclosed embodiments of the '286 patent, the individual chips are held in a heated chuck and engaged with the tip ends of the leads so that bonding materials such as eutectic bonding alloys, solders or the like carried on the chip or on the leads are activated to form bonds between the chip and the leads. As also disclosed in certain embodiments of the '286 patent, and in certain embodiments of commonly assigned U.S. Pat. No. 5,766,987, the disclosure of which is hereby incorporated by reference herein, a covering layer may be provided over the rear surfaces of the chips so as to protect the rear surfaces of the chips from encapsulant contamination during the process.
The processes provided by the aforementioned patents provide substantial improvements in the art. Nonetheless, even further improvement would be desirable. For example, the heat applied during a bonding process may cause polymeric layers incorporated in components such as interposers to expand, making it more difficult to achieve precise alignment between the conductive features of the microelectronic elements and the conductive features of the connection component. Certain bonding materials, particularly solders, require fluxes at the connections to make a sound joint. These fluxes can cause problems in service unless they are removed by a cleaning process, which adds cost to the process. Also, many of the techniques commonly used in dispensing solder onto parts to be assembled do not lend themselves to extremely fine-pitch assembly work. Therefore, further improvements in bonding processes and in processes for applying bonding materials such as solders would be desirable.
SUMMARY OF THE INVENTION
One aspect of the present invention provides improved processes for making electrically conductive bonds between microelectronic components. In preferred processes according to this aspect of the invention, bonds such as solder joints are formed between contacts on a first microelectronic element such as a semiconductor chip or wafer and conductive elements of a second microelectronic element such as a connection component, by momentarily heating the first microelectronic element so as to activate a bonding material and then allowing the first microelectronic element to cool, leaving the contacts on the first microelectronic element bonded to conductive features on the second element or connection component. In preferred processes according to this aspect of the invention, the second element or connection component is maintained at an average temperature below the average temperature of the first microelectronic element during the momentary heating step. Stated another way, the temporary heating steps is performed so that the bonds are formed while the first microelectronic element is at a higher temperature than the second element or connection component. The microelectronic elements are not in thermal equilibrium with one another. Most preferably, where the second element or connection component includes a
Haba Belgacem
Wolter Klaus-Jurgen
Lerner David Littenberg Krumholz & Mentlik LLP
Picardat Kevin M.
Tessera Inc.
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