Johnson counter circuit with invalid counter position detection

Details Johnson counter circuit with invalid counter position detection Johnson counter circuit with invalid counter position detection

1989-02-08

1991-02-12

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

377 34, 377 56, H03K 2700, H03K 2140

Patent

active

049930516

ABSTRACT:
An end-around coupled chain of n bit counter stages, including an inversion element in the chain, employs a detection/correction mechanism for an invalid counter position. A "1,0" state pair is detected in the highest order two bit stages and the simultaneous occurrence of any "1" state in an adjacent group of at least J stages (where J equals the integer part of the number of stages divided by three) indicates an invalid counter position. At least said adjacent group of bit stages is set to "0" in response to the detection of an invalid counter position.

REFERENCES:
patent: 3530284 (1970-09-01), Wood
patent: 3555249 (1971-01-01), Altrons
patent: 3909729 (1975-09-01), Fry
patent: 4493095 (1985-01-01), Yazawa
patent: 4568841 (1986-02-01), Mayhew
patent: 4839909 (1989-06-01), Warner
K. S. Hall, "Modified Twisted-Ring Counter Circuit", IEEE Transactions on Computers, Jun. 1969, p. 568.
C. vanHolten, "Digital Dividers With Symmetrical Outputs", Wireless World, vol. 88, No. 1559, Aug. 1982, pp. 43-46.
G. L. Douglas, "Walking Counter Synchronization Scheme", IBM Technical Disclosure Bulletin, vol. 15, No. 6, Nov. 1972, pp. 1848, 1949.
P. M. Overfield, "Error Correction in Johnson Counters", New Electronics, vol. 13, No. 11, May 27, 1980, p. 38.

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