JMOS transistor utilizing polysilicon sinks

Details JMOS transistor utilizing polysilicon sinks JMOS transistor utilizing polysilicon sinks

1987-10-20

1989-03-07

LaRoche, Eugene R.

357 234, 357 237, 357 59, H01L 2978, H01L 2980

Patent

active

048110639

ABSTRACT:
JMOS depletion mode transistors include back-to-back junctions in the doped polysilicon layer that serves as the gate. The polysilicon layer includes a first region of the same conductivity type as the channel in contact with the channel, and a second region, of the same conductivity type as the channel and to which the gate potential is applied, spaced apart by a region of the opposite conductivity type that serves as a sink for minority carriers in the channel. Both buried oxide layer and recessed gate JMOS transistors are included.

REFERENCES:
patent: 4259681 (1981-03-01), Nishizawa
patent: 4470059 (1984-09-01), Nishizawa et al.
patent: 4543595 (1985-09-01), Vora
patent: 4611220 (1986-09-01), MacIver
patent: 4641164 (1987-03-01), Dolny et al.
patent: 4644386 (1987-02-01), Nishizawa et al.
patent: 4658378 (1987-04-01), Bourassa
patent: 4746960 (1988-05-01), Valeri et al.

Affiliated with

Also associated with

Rating

JMOS transistor utilizing polysilicon sinks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with JMOS transistor utilizing polysilicon sinks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and JMOS transistor utilizing polysilicon sinks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1672637