Pulse or digital communications – Receivers
Reexamination Certificate
2000-07-28
2004-01-20
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Receivers
C375S371000
Reexamination Certificate
active
06680982
ABSTRACT:
BACKGROUND OF THE INVENTION
This application incorporates by reference Taiwanese application Serial No. 88115692, Filed Sep. 10, 1999
FIELD OF THE INVENTION
The invention relates in general to a jitter-tolerant signal receiver and a method of designing a jitter-tolerant signal receiver, and more particularly to a jitter-tolerant signal receiver applied in a communication system of two different clock domains.
DESCRIPTION OF THE RELATED ART
Communication systems consisting of a transmitter and receiver have a common problem of incompatibility of their respective frequency domains. The system clock of the transmitter differs from that of the receiver in frequency or phase. As a result, a Phase Lock Loop (PLL) is used to recover the clock of the transmitter in the receiver. Therefore, a receiving clock is generated, which has the same frequency but probably different phase as compared to the system clock of the receiver. Thus, the sampling of data and transmission of data signal can be easily performed.
In the receiver, the regular system clock can be obtained by first producing a regular unit clock using crystal oscillation and then directly dividing the resulting regular unit clock. The unit clock is used to lock the incoming data and the system clock is used for clocking logic circuit. However, the receiving clock generated by the PLL often suffers from severe jitters due to clock drift. This jitter in the receiving clock may result in data loss and so the prevention of data loss due to jitter is an important subject nowadays.
Referring to
FIG. 1
, a block diagram of a traditional signal receiver is illustrated. An input signal VIN is inputted to an input terminal D
11
of D flip-flop
102
, and a receiving clock RXCLK is inputted to a clock input terminal CK
11
of D flip-flop
102
. The input signal VIN is sampled at the rising edge of the receiving clock RXCLK and an event signal EVNT of the same logic level as the input signal VIN is outputted from an output terminal Q
11
of D flip-flop
102
. Next, the event signal EVNT is inputted into an input terminal D
12
of D flip-flop
104
, and a system clock SCLK is inputted to a clock input terminal CK
12
of D flip-flop
104
. A sampling event signal SEVNT is then outputted from an output terminal Q
12
of D flip-flop
104
. These D flip-flops, for example, are of positive edge-triggered.
FIG. 2
is a timing diagram of the signal receiver in FIG.
1
. Referring to FIG.
1
and
FIG. 2
at the same time, a unit clock UCLK, which can be produced by crystal oscillation, is divided to produce a system clock SCLK. As the receiving clock RXCLK changes from low level to high level, the D-flip-flop
102
transfers the input signal VIN to the event signal EVNT. At t
201
, for example, the D-flip-flop
102
transfers the high level input signal VIN to the event signal EVNT at the rising edge of the receiving clock RXCLK, which changes from low to high.
Similarly, when a rising edge of the system clock SCLK occurs, the event signal EVNT is transferred to the sampling event signal SEVNT and then the sampling event signal SEVNT holds for a period of the system clock SCLK in the D flip-flop
104
. At t
202
, for example, upon a rising edge of system clock SCLK, the high level event signal EVNT is transferred to the sampling signal SEVNT which is then retained at the same level with the event signal EVNT for a period of system clock SCLK.
Therefore, through the D flip-flop
102
, the input signal VIN is transferred to the event signal EVNT which has the same period as the receiving clock RXCLK. After processing the event signal EVNT through the D flip-flop
104
, a sampling event signal SEVNT with the same period as the system clock SCLK is obtained.
However, an event, which represents logic
1
of the corresponding signal, can be lost due of the occurrence of jitters in the clock. For example, when a jitter occurs in the receiving clock RXCLK, the event of event signal EVNT may be retained at a high level only for a short moment, say from t
204
to t
205
. As a result, the event of event signal EVNT, which is retained at high level from t
204
to t
205
, can not be sampled at t
203
or t
206
and can not be transferred to the sampling event signal SEVNT. The event of event signal EVNT is thus lost.
One of traditional methods for solving this problem is to use a signal receiver with four D flip-flops. Referring to
FIG. 3
, the block diagram of a traditional jitter-tolerant signal receiver is illustrated. First, a receiving signal RXCLK is fed to the clock terminals CK
31
, CK
32
, and CK
33
of D flip-flop
302
,
304
, and
306
respectively. Next, an input signal VIN is applied to the input terminal D
31
, and an event signal EVNT
1
is outputted from an output terminal D
31
in the D flip-flop
302
. The event signal EVNT
1
is then fed to the input terminal D
32
, and an event signal EVNT
2
is outputted from the output terminal Q
32
in the D flip-flop
304
. Following that, the event signal EVNT
2
is applied to a input terminal D
33
, and an event signal EVNT
3
is outputted from a output terminal Q
33
in D flip-flop
306
. Aside from the event signal EVNT
3
being inputted to the input terminal D
34
, a system clock SCLK is fed to the clock terminal CK
34
in the D flip-flop
308
simultaneously. Finally, the output terminal Q
34
of the D flip-flop
308
outputs a sampling event signal SEVNT that is transferred from the input signal VIN.
FIG. 4
is the timing diagram of the traditional jitter-tolerant signal receiver in FIG.
3
. Referring to FIG.
3
and
FIG. 4
at the same time, at t
401
, the input signal VIN of high level is transferred to the event signal EVNT
1
which retains it in high level for the period of receiving signal RXCLK in the D flip-flop
302
. Due to a jitter in the receiving clock RXCLK starting at t
403
, the event signal EVNT
1
can only be sustained in high level for the period of the jitter. In D flip-flop
304
and
306
, the event signal EVNT
2
is retained in low level and the event signal EVNT
3
is retained in high level only for the period of the jitter.
However, at t
403
, the period of the event of event signal EVNT
3
is too short to be sampled by the D flip-flop
308
at the adjacent positive edge of t
402
and t
4
O
4
. So the event is lost when transferred to the sampling event signal SEVNT in D flip-flop
308
.
Another method of solving this problem is to add an OR gate to avoid missing signals in FIG.
3
. Referring to
FIG. 5
, which is a block diagram of another traditional jitter-tolerant receiver, the event signal EVNT
2
and event signal EVNT
3
are fed to an OR gate
510
and an OR signal (OREVNT) is then outputted from the OR gate
510
and applied to an input terminal D
34
in the D flip-flop
308
.
The timing diagram of the traditional jitter-tolerant receiver in
FIG. 5
is illustrated in FIG.
6
. The OR signal OREVNT results from an OR operation on the event signals ENVN
2
and EVNT
3
. However, if the events in input signal VIN are too close to each other, the events transferred from the input signal VIN to OR signal OREVNT might be indistinguishable. An example is diagrammed in
FIG. 6
; after t
601
, the OR signal OREVNT is in high level for more than ten periods of unit clock UCLK. Similarly, the sampling event signal SEVNT is in high level after t
602
. Two events in the input signal VIN are combined to one event in the sampling event signal SEVNT and indistinguishable from each other. Consequently, more complicated circuit is needed to handle this type of situations. If the jitter becomes more severe or a receiving clock RXCLK of lower frequency is used, the logic circuit needed would be more difficult to be designed.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a jitter-tolerant signal receiver and a method of designing a jitter-tolerant signal receiver, requiring only three D flip-flops. Thus, the jitter can be eliminated and data transmitting and receiving can be accomplished accurately. The number of components in the invention is fe
Bocure Tesfaldet
Via Technologies Inc.
LandOfFree
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