Jitter-resistive delay lock loop circuit for locking delayed...

Details Jitter-resistive delay lock loop circuit for locking delayed... Jitter-resistive delay lock loop circuit for locking delayed...

2007-06-26

2007-06-26

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

11463897

ABSTRACT:
A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit and the reference clock for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

REFERENCES:
patent: 5838179 (1998-11-01), Schmidt
patent: 6069507 (2000-05-01), Shen et al.
patent: 6842399 (2005-01-01), Harrison

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