Jitter reduction circuit for frequency synthesizer

Details Jitter reduction circuit for frequency synthesizer Jitter reduction circuit for frequency synthesizer

1983-01-31

1985-08-20

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 17, 331 25, H03L 718

Patent

active

045367183

ABSTRACT:
A frequency synthesizer of the type employing a cycle cancellation technique and providing a correction signal which at least reduces the jitter in the output frequency caused by each cancelled cycle. A control device (CD) causes cycles to be added (PA) and cancelled (PS) without affecting the average frequency (Fc). A compensation signal for the resultant jitter is also generated (DAC and I) which is combined with the correction signal in an adder (AS) and with the frequency control voltage signal from the phase comparator (PC) in a further adder (ASD).

REFERENCES:
patent: 4179670 (1979-12-01), Kingsbury
patent: 4380743 (1983-04-01), Underhill et al.
patent: 4468632 (1984-08-01), Crowley

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