Jitter reduction circuit

Details Jitter reduction circuit Jitter reduction circuit

2000-07-20

2002-04-16

Mis, David (Department: 2817)

Oscillators

Ring oscillators

C331S034000, C331S17700V, C327S281000, C327S288000

Reexamination Certificate

active

06373342

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to voltage controlled oscillators (VCO) and similar circuits which suffer from “jitter” problems caused by a circuit delay and more specifically to the control of this delay element by means of a new trip point control delay circuit and/or by means of selectable capacitor charging current sources.
2. Description of the Related Art
The delay element in many typical VCO and/or similar circuits uses a current charging capacitor circuit, shown schematically in
FIG. 1
a.
This basic circuit is comprised of a current source
1
, a capacitor
2
, and a control transistor
3
. When the input voltage V
in
is such as to turn “OFF” the transistor
3
, current (I) from current source
1
will charge the capacitor
2
. Likewise, when input voltage V
in
is such as to turn “OFF” the transistor
3
, current (I) from current source
1
will flow through transistor
3
and capacitor
2
will discharge.
The basic circuit of
FIG. 1
a
is an inverter since it's output is complementary to it's input.
FIG. 1
b
illustrates the inverter symbol
4
used to represent this circuit in this patent.
FIG. 1
c
shows a timing diagram for the circuit of
FIG. 1
a
for the case where input voltage V
in
goes “LOW”, relative to the threshold voltage, turning “OFF” transistor
3
. The output V
out
is determined by the charging rate of the capacitor
2
, as shown with a relative slow rise time depending on the circuit's time constant.
FIG. 2
shows the basic inverter circuit of
FIG. 1
as used in one application; e.g., a voltage controlled oscillator (VCO). The circuit consists of three inverters
5
-
7
and three charging capacitors
8
-
10
. The output of the first inverter
5
is coupled to capacitor
8
and to the input of the second inverter
6
. Similarly, the output of inverter
6
is coupled to capacitor
9
and to the input of inverter
7
. Finally, the output of the third inverter
7
is coupled to capacitor
10
and is also fed back to the input of inverter
5
. The circuit output is taken off capacitor
10
at the output of inverter
7
. The frequency of this oscillator is determined by the output signal slew rate, which is largely determined by the charging and discharging rate of the capacitors.
A problem often associated with a circuit like that of
FIG. 2
, is one of “jitter”, caused by a threshold band where the input voltage V
in
is applied to the control transistors.
FIG. 3
a
illustrates that for rather slow switching times there can be a relatively large amount of uncertainty, known as “jitter”, in the circuit's response.
FIG. 3
b
illustrates the desired relationship between the transistor threshold and output slew rate to provide substantially less “jitter” in the circuit.
SUMMARY OF THE INVENTION
A circuit for improving the performance of a charging capacitor inverter, used in voltage controlled oscillators (VCO's) and other similar circuits, is disclosed. The techniques used include both trip point control and charging current control to improve the response time of the circuit and to reduce the amount of “jitter” in the circuit.
In the first approach, an in-line transistor is placed between the node of the capacitor of a typical current charging capacitor circuit and the output. The threshold of this transistor is controlled by a dc bias level (control voltage) which allows this transistor to turn “ON” or “OFF” when the node voltage of the capacitor reaches a controllable preset level. The slew rate of the circuit's output is increased considerable by means of a “pull-UP/DOWN” transistor coupled to the output. As a result, the “jitter” in the circuit is significantly reduced. In addition, the circuit delay can be further controlled changing the capacitor charging current in the circuit.
Two embodiments of the invention are disclosed; the first covering the fundamental trip point voltage control approach, and the second incorporating both current delay control and trip point delay control in the same circuit to provide for both fine and coarse adjustment of the delay in the circuit.
The improvements of this invention will positively impact applications such as, but not limited to, voltage controlled oscillators, delay lines, DRAMs, microprocessors, and latches.


REFERENCES:
patent: 4804929 (1989-02-01), Kato et al.
patent: 5594391 (1997-01-01), Yoshizawa
patent: 5666088 (1997-09-01), Penza
patent: 6137371 (2000-10-01), Fukaishi

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