Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Phase comparison
Reexamination Certificate
2001-01-29
2003-02-18
Le, N. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Phase comparison
C324S076520, C702S010000
Reexamination Certificate
active
06522122
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a jitter measuring device and method for measuring on-time-base fluctuations in one or both of the rise and fall of a signal which has a periodic waveform, such as a pulse train in digital transmission or a clock signal that is output from a semiconductor integrated circuit.
For example, pulses in digital transmission are properly arranged on the time base when generated, that is, the pulse train has a waveform that rises and falls in synchronization with a clock of an exact period, but its passage through a regenerative repeater or the like causes fluctuations in the pulse arrangement, that is, pulse jitter. When the amount of jitter is large, noise will increase, leading to improper transmission or malfunction of equipment. Accordingly, it is necessary to measure and take into account the amount of jitter in the case of handling signals of periodic waveforms.
A conventional jitter measuring device is disclosed in Japanese Patent Application Laid-Open Gazette No. 262083/96 entitled “Jitter Measuring Device.” In the conventional jitter device, as depicted in
FIG. 1
, a signal to be measured
23
from a device under measurement
11
, such as a regenerative repeater or semiconductor integrated circuit, is provided via an input terminal
12
to a PLL (Phase-Locked Loop) circuit
13
and a sampling circuit
14
. In the PLL circuit
13
the oscillation output from a VCO (Voltage-Controlled Oscillator)
15
is frequency-divided by a frequency divider
16
down to 1/N, and the frequency-divided signal is phase-compared by a phase comparator
17
with the signal
23
fed from the input terminal
12
. The phase-compared output is added by an added
18
with a phase offset voltage fed from a D/A converter
19
, and the added output is provided via a loop filter
21
to a control terminal of VCO
15
. The above-mentioned phase offset voltage is adjusted so that the oscillation frequency of VCO
15
becomes N times higher than an average value of the frequency of the signal to be measured
23
and that the phase of the sinusoidal oscillation output from VCO
15
coincides at its substantially zero-crossing point with the rise of the signal
23
.
The sinusoidal output from the PLL circuit
13
is applied to a harmonic suppressor filter
22
, wherein its higher harmonics are suppressed to form a signal of a pure sinusoidal waveform. This sine-wave signal is applied to the sampling circuit
14
, wherein it is sampled by, for instance, the leading edge of the signal to be measured
23
, and the output from the sampling circuit
14
is converted by an A/D converter
24
to digital data, which is once stored in a memory
25
. When the input signal to be measured
23
has no jitter, the digital data is representative of a sample value of the sinusoidal VCO output at the zero-crossing point thereof. If the input signal to be measured
23
has jitter, the digital data that is stored in the memory
5
will be sample data of the amplitude of the sinusoidal VCO output at a point displaced apart in phase from the zero-crossing point of the VCO output by a value corresponding to the amount of jitter. Letting the VCO output signal be represented by Y(t)=A sin (2&pgr;Nf
i
t) (where f
i
is the frequency of the signal to be measured
23
), the voltage obtained by sampling the VCO output signal Y(t) can be expressed by v(t
a
)=A sin (2&pgr;Nf
i
.T
j
(t
n
)) (where n=0, 1, 2, . . . ), and T
j
(t
n
) is data indicating the jitter and can be calculated by T
j
(t
n
)=(1/2&pgr;Nf
i
)sin
−1
(v(t
n
)/A). This calculation is conducted in a calculation part
26
, and the data T
j
(t
n
) is displayed intact or its square mean value T
jrms
is displayed as an effective value in a display part
27
. It is also possible, in this case, to calculate and display a square mean value T
jrms
={square root over ((&Sgr;(t
j
(t
i
)−T
jm
))
2
)} that is the difference between a mean value T
jm
of T
j
(t
n
) over a certain period of time and T
j
(t
n
).
The fabrication of the conventional jitter measuring device is troublesome because it is necessary that the PLL circuit
13
and the harmonic suppression filter
22
for stably generating the sine-wave signal at an average frequency of the signal to be measured
23
be designed and fabricated for each different signal to be measured. For high-accuracy measurement, the phase of the sinusoidal VCO output needs to be adjusted by a phase offset voltage from the D/A converter
19
so that the VCO output is sampled at its zero-crossing point when the signal
23
has no jitter—this phase adjustment is difficult to make.
In view of the above, it is possible to use a jitter measuring device depicted in
FIG. 2. A
reference signal of an exact period is applied from a reference signal generator
31
to the device under measurement
11
, from which a jitter-affected, square-wave signal to be measured
23
, which has an average frequency equal to the frequency of the reference signal, is applied to a sampling circuit
14
. The reference signal is applied as well to a signal generator
32
, which generates a sampling clock that has a frequency equal to 1/N of an average frequency of the signal to be measured
23
and coincides with the midpoint or zero-crossing point of the leading or trailing edge of a signal corresponding to the average frequency of the square-wave signal to be measured
23
. The sampling clock is used to sample the signal
23
by the sampling circuit
14
. That is, as indicated by the white circles in
FIG. 3A
, the square-wave signal to be measured
23
is sampled, for example, in the vicinity of the zero-crossing point of its leading edge by the sampling clock depicted in
FIG. 3B
as indicated by the white circles in FIG.
3
A.
In order that the signal to be measured
23
and the sampling clock may bear such a phase relationship, the following processing is carried out. That is, the output frequency of the signal generator
32
is set at a value such that the N-fold value of the frequency of the sampling clock slightly differs from the average frequency of the signal to be measured
23
. By this setting, the sampling point of the signal
23
by the sampling clock gradually shifts; for example, while the low-level portion of the square-wave signal
23
is sampled, the level of the output sample from the sampling circuit
14
has a large negative value, but when the phase of sampling the signal
23
by the sampling clock gradually lags and then the sampling point reaches the leading edge of the square-wave signal
23
as indicated by the while circles in
FIG. 3C
, the level of the output sample gradually approaches zero. When the point in time the level of the output sample becomes zero is detected by a phase detector
33
, the detected output is provided to the signal generator
32
. In response to the input thereto, the signal generator
32
sets its output frequency such that it generates a sample clock that retains the phase of sampling at that point in time and has a frequency equal to 1/N of the average frequency of the signal to be measured
23
.
Further, the output from the phase detector
33
at that time is applied to the sampling clock control circuit
34
to control it to permit the passage therethrough of the sampling clock from the signal generator
32
to the A/D converter
24
. As a result, the A/D converter
24
starts, at this point in time, the conversion of the output sample from the sampling circuit
14
to digital data corresponding to its level for each sampling clock. The thus converted digital data is stored in the memory
25
.
Upon completion of the required digital data, the amount of jitter is calculated for each piece of digital data. That is, when the sampling point displaced from the ideal zero-crossing point of the waveform of the signal
23
by J
i
and the digital data of that sample is V
i
as depicted in
FIG. 4
, the amount of jitter j
i
can be calculated by J
i
=V
i
/tan &agr; since V
i
and J
i
bear a relationship t
Ando Akihiko
Miyaji Yuichi
Watanabe Toshifumi
Advantest Corporation
Gallagher & Lathrop
Kerveros James
Lathrop, Esq. David N.
Le N.
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