Pulse or digital communications – Testing – Phase error or phase jitter
Reexamination Certificate
1999-04-20
2001-09-25
Vo, Don N. (Department: 2631)
Pulse or digital communications
Testing
Phase error or phase jitter
C375S375000, C375S376000, C327S160000
Reexamination Certificate
active
06295315
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system and method for measuring time jitter in periodic signals and, in particular, to such a system and method that are suited to built-in self test applications for phase-locked loops.
BACKGROUND AND SUMMARY OF THE INVENTION
Phase-locked loops (PLLs) are used in a wide variety of applications including frequency synthesis, timing recovery, clock distribution, and phase demodulation. These applications are sometimes employed, for example, in optical fiber links, wireless telephones, and computers. In many of these applications, timing variations or jitter characteristics of a PLL can significantly affect the performance of the PLL and the application in which the PLL is used.
With reference to timing or clock recovery, for example, a PLL may be used to recover a clock signal from a serial data stream. As the signal-to-noise ratio of a data stream decreases, the recovered clock signal can have timing variations or “jitter.” A jittery clock signal can introduce errors in the reading of the serial data stream, thereby increasing the bit error rate for the data stream. As a result, measuring the performance of a PLL in terms of its jitter can be important to providing accurate clock recovery and lower bit error rates.
As another example, some large integrated circuits include PLLs for clock generation. The PLL may provide a clock signal that is phase-shifted relative to a supply clock signal. Accurate operation of such an integrated circuit can require that the PLL provide the phase-shifted clock signal without jitter.
Accurate measurement of jitter characteristics, including jitter characteristics of PLLs, is needed for a wide variety of applications. Moreover, with PLLs increasingly being incorporated into larger-scale integrated circuits, jitter measurement components suitable for built-in self test applications are also desirable. While some jitter measurement components suitable for built-in self test applications are available, their design limits their resolution to the period of about one gate delay of the process used to build the circuit (e.g., 100-200 picoseconds for CMOS-based circuits). With signals having frequencies on the order of 100 MHz, such a jitter measurement resolution is no better than 1 percent of the signal period. Such a resolution can be inadequate.
The present invention provides, therefore, a jitter measurement system for measuring timing variations or “jitter” in a periodic signal waveform as provided, for example, by a PLL. In one implementation a PLL receives a periodic input signal waveform F
REF
and generates a periodic output signal waveform F
VCO
with a frequency and phase that correspond to the input signal F
REF
. The jitter measurement system measures jitter in the output signal waveform F
VCO
.
In one implementation, the jitter measurement system includes a period gate generator that generates a gate signal with the instantaneous period of the output signal waveform F
VCO
. The gate signal includes a leading edge and a trailing edge and is delivered to a pair of triggered oscillators that provide respective oscillator output signals with substantially matched frequencies. The oscillators are triggered at the respective leading and trailing edges of the gate signal. The oscillator output signals are delivered to respective oscillation counters and to a coincidence detector. The oscillation counters count the periods of the respective oscillator output signals from when they are triggered until the coincidence detector detects coincidence between the signals (e.g., coincidence between the trailing edges of the signals). A period measurement of the output signal waveform F
VCO
is determined from the counts obtained by the oscillation counters. Multiple such period measurements are obtained to provide information representing jitter in the output signal waveform F
VCO
.
With measurements based upon coincidence between them, the oscillator output signals function together as a vernier scale that provides high resolution period measurements. The extent to which the frequencies of the oscillator output signals are matched determines the resolution with which the jitter measurement system can measure the period of the output signal waveform F
VCO
and hence its jitter. The frequencies are substantially matched in that they differ by less than 1 percent and, in some implementations, by {fraction (1/10)} percent or less. For example, oscillator output signals having frequencies that are about 100 MHz to within {fraction (1/10)} percent are capable of period measurements to a resolution of about 10 picoseconds. Such a resolution is an order of magnitude better than that of available jitter measurement systems that are suitable for built-in self test (BIST) and automatic test equipment (ATE) applications.
Additional objects and advantages of the present invention will be apparent from the detailed description of the preferred embodiment thereof, which proceeds with reference to the accompanying drawings.
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B.R. Veillette and G.W. Roberts, On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops, IEEE Journal of Solid-State Circuits, vol. 33, No. 3, pp. 483-491, Mar. 1998.
Internet document: http://www.logicvision.com/solution/pllbist.htm—undated.
Frisch Arnold M.
Rinderknecht Thomas H.
Ipsolon LLP
Vo Don N.
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