Jitter-free divider

Details Jitter-free divider Jitter-free divider

2009-03-17

2010-10-12

Lam, Tuan (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

07813466

ABSTRACT:
A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.

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