Jitter-corrected spectrum analyzer

Details Jitter-corrected spectrum analyzer Jitter-corrected spectrum analyzer

2001-12-21

2003-11-18

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C702S076000, C702S077000, C702S089000, C702S079000, C324S076190, C324S076210, C324S076220

Reexamination Certificate

active

06651016

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a spectrum analyzer for processing data obtained by periodically digitizing an analog signal to determine the signal's frequency spectrum, and in particular to a spectrum analyzer that compensates for errors arising from jitter in a clock signal controlling digitization timing.
2. Description of Related Art
FIG. 1
illustrates a prior art spectrum analyzer
10
for producing an output digital data sequence (“vector”) H representing the amplitude and phase of the various frequency components of an analog input signal (INPUT). Spectrum analyzer
10
includes an A/D converter
14
for digitizing the INPUT signal in response to leading edges of successive pulses of a CLOCK signal produced by a clock signal generator
16
. Trailing edges of the CLOCK signal tell an acquisition memory
20
to store each data value A/D converter
14
produces. After N CLOCK signal cycles, acquisition memory
20
will contain an N-element vector A={A
0
. . . A
N−1
} representing the INPUT signal magnitude sampled at intervals T seconds apart where T is the period of the CLOCK signal. A computer
22
then reads the time domain vector out of acquisition memory
20
and subjects it to a discrete Fourier transform (DFT) function or a fast Fourier transform (FFT) function to produce an N/2+1 element vector of complex numbers H {H
0
. . . H
N/2
} where each number indicates a magnitude and phase of a separate frequency component of the INPUT signal.
Since the FFT or DFT function
24
uses the period T of the CLOCK signal as an input parameter, the accuracy with which the output vector H characterizes the frequency spectrum of the INPUT signal depends in part on the accuracy with which clock signal generator
16
generates each CLOCK signal edge.
FIG. 2
illustrates a prior art clock signal generator
16
for producing a CLOCK signal having an adjustable period. A reference oscillator
30
produces a high frequency reference signal ROSC of stable period P that is successively delayed by a series of L logic gates
32
to produce a set of tap signals TAP
0
−TAP
L−1
. A delay lock loop (DLL) controller
38
compares the phase of the TAP
L−1
signal to the ROSC signal and adjusts the switching delay of each gate
32
so that TAP
L−1
is in phase with the ROSC signal, thereby ensuring that the average delay of each gate
32
is P/L. Thus each tap signal TAP
0
−TAP
L−1
will have the same period P as the ROSC signal, but the tap signals will be distributed in phase. A multiplexer
34
, controlled by a vector SEL from a pattern generator
36
, produces the output CLOCK signal by selecting edges of tap signals TAP
0
−TAP
L−1
. Pattern generator
36
produces a next element of its SEL output vector in response to each edge of the ROSC signal. Pattern generator
36
controls the period of the CLOCK signal by the order in which it signals multiplexer
34
to select tap signal edges to be delivered to its output as CLOCK signal edges.
For example suppose L=4 so that each gate
32
has a nominal delay of P/4 and, we want clock signal generator
16
to produce eight CLOCK signal edges with a period 5P/4 between edges as illustrated in FIG.
3
. Then pattern generator
36
can be programmed to respond to a set of 10 ROSC signal edges by generating the following SEL vector:
SEL={0,1,2,3
, X,
0,1,2,3
, X}
The numbers indicate which tap signal is to be selected in response to successive ROSC signal edges. An “X” indicates that pattern generator
36
tells multiplexer to select none of its input tap signals TAP
0
−TAP
3
. As shown in
FIG. 3
, the above SEL vector causes multiplexer
34
to respond to the first four ROSC signal edges by selecting each tap signal TAP
0
−TAP
3
in turn to provide an edge of the output CLOCK signal. Multiplexer
34
responds to the fifth ROSC edge by selecting none of the tap signals to provide a CLOCK signal edge. The same pattern is repeated for the next five ROSC signal edges. Thus the clock signal generator
16
produces eight CLOCK signal edges 5P/4 seconds apart in response to ten ROSC signal pulses P seconds apart.
One problem with the clock signal generator
16
of
FIG. 2
is that while gates
32
may be-of similar design and implemented on the same integrated circuit chip, and while all gates
32
may be controlled by the same control signal output of DLL controller
38
, all gates
32
will have slightly different delays due to process variations between the gates. While DLL controller
38
ensures that the sum of the gate delays will be P and that the average delay of each gate will be P/L, some gates
32
will have switching delays slightly larger than P/L and some will have delays smaller than P/L.
A clock signal is said to be “jittery” when the clock signal has some constant average period T between edges over a number of clock signal cycles, but the actual period between them tends to vary from edge-to-edge. A clock signal has “random jitter” when the edge timing error changes randomly from edge-to-edge. Random jitter typically arises from system noise. A clock signal has “periodic jitter” when the edge timing variation is periodic. In a periodically jittery clock signal having an average period T and a periodic jitter of MT, for all values of 0≦K<M, an actual timing of each K
th
clock signal edge and every M
th
edge thereafter differs by a similar amount JITTER
K
from a nominal timing each edge would have had if the clock signal had a constant period T between edges.
In the example illustrated in
FIG. 3
every edge of tap signal TAP
0
has the same error, JITTER
0
. Since the first and every 4th edge of the clock signal thereafter is derived from tap signal TAP
0
, then the first and every 4th edge of the clock signal has the same timing error, JITTER
0
. More generally, since all edges of the Kth tap signal T
K
(for K=0 to 3) have the same timing error JITTER
K
, and since the Kth edge of the clock signal and every 4th edge thereafter is derived from an edge of the K
th
tap signal, then the K
th
edge of the clock signal and every 4
th
edge thereafter has the same timing error, JITTER
K
. The clock signal produced by clock signal generator
16
is therefore periodically jittery and the jitter has a period TM, where M=4 in the above example.
The edge timing errors in the clock signal produced by timing signal generator
16
are not only periodic, they are also predictable. If we measure the delay of each gate
32
, and we know in advance which tap signal TAP
0
−TAP
M−1
will produce each edge of the clock signal, then we can predict the timing error in each clock signal edge. Y. C. Jenq, in a paper entitled “Sampling Clocks Based on High-Resolution Timing Unit” published Nov. 3, 2000, teaches that it is possible to modify the DFT function of
FIG. 1
to take into account the predictable jitter error in each clock signal edge so that the DFT function produces an output vector H accurately representing the frequency spectrum of the A/D converter's analog INPUT signal. While Jenq's modified DFT function eliminates the effects of periodic jitter in the clock signal on the output vector H, the complex modified DFT function requires a relatively large amount of processing time.
What is needed is a less computationally intensive method for processing an A/D converter output vector to produce a vector representing the frequency spectrum of the A/D converter's analog input signal, wherein errors arising from predictable periodic clock signal jitter are substantially eliminated.
BRIEF SUMMARY OF THE INVENTION
An analog signal is digitized by an analog-to-digital (A/D) converter clocked by edges of a periodically jittery clock signal to produce an output digital data sequence (vector) A in which each successive data element represents an amplitude of the analog signal at the time of occurrence of a corresponding o

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