Jitter control processor and a transceiver employing the same

Details Jitter control processor and a transceiver employing the same Jitter control processor and a transceiver employing the same

2006-01-10

2006-01-10

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

C375S219000, C375S363000, C375S364000, C370S505000

Reexamination Certificate

active

06985550

ABSTRACT:
The present invention provides a transceiver couplable to a communications network having a jitter control processor and methods of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a transmitter stage that controls a transmit signal. In one embodiment, the transmitter stage includes a transmit time error measurement system configured to generate a transmit time error signal as a function of timing synchronization associated with a communications network clock and a transceiver master clock, a transmit filter circuit configured to develop a filtered time error signal as a function of the transmit time error signal, and a stuffing control system configured to insert a stuffing control signal into the transmit signal as a function of the transmit time error signal and the filtered time error signal.

REFERENCES:
patent: RE34206 (1993-03-01), Sayar
patent: 5574756 (1996-11-01), Jeong
patent: 6327666 (2001-12-01), Langberg et al.
“Multirate Systems and Filter Banks,” P.P. Vaidyanathan, Prentice Hall Signal Processing Series: Chapter 5. Section 5.3: pp. 211-213: Jul. 1992.

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