Jitter control circuit having signal delay device using CMOS sup

Details Jitter control circuit having signal delay device using CMOS sup Jitter control circuit having signal delay device using CMOS sup

1989-12-08

1990-09-11

Richardson, Robert L.

Facsimile and static presentation processing

Facsimile

Recording apparatus

358325, 358326, 358342, 360 26, 360 361, 369 59, H04N 989

Patent

active

049567209

ABSTRACT:
A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

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Patent Abstracts of Japan, vol. 7, No. 200, E196, 9/3/83, JP-5899035, 6/13/83.
Patent Abstracts of Japan, vol. 8, No. 173, E259, 8/9/84, JP-5966218, 4/14/84.

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