Jitter attenuation with a fractional-N clock synthesizer

Details Jitter attenuation with a fractional-N clock synthesizer Jitter attenuation with a fractional-N clock synthesizer

2011-07-26

2011-07-26

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S016000, C375S376000

Reexamination Certificate

active

07986190

ABSTRACT:
A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.

REFERENCES:
patent: 5038117 (1991-08-01), Miller
patent: 6993306 (2006-01-01), Buznitsky et al.
patent: 7106244 (2006-09-01), Hsu
patent: 7158596 (2007-01-01), Knapp et al.
patent: 7253842 (2007-08-01), Louie et al.
patent: 7272202 (2007-09-01), Knapp et al.
patent: 7339628 (2008-03-01), Gudmondson et al.
patent: 7558358 (2009-07-01), Melanson

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