Jitter and load insensitive charge transfer

Details Jitter and load insensitive charge transfer Jitter and load insensitive charge transfer

1999-08-27

2002-09-17

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S154000

Reexamination Certificate

active

06452531

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to charge transfer in electronic circuits, and more particularly, to methods and apparatus for transferring a quantity of charge to or from a load during a transfer interval, wherein the charge transferred is significantly insensitive to load characteristics and variations in the transfer interval.
BACKGROUND OF THE INVENTION
A variety of applications require a controlled transfer of electrical charge to or from a load. The load may be, for example, an electrical, electronic, or electro-mechanical device. In particular, the load may be a circuit or a portion of a circuit that performs some function based on the transferred charge.
Various charge transfer circuits are known for particular applications. In general, conventional charge transfer circuits employ some type of switching mechanism to control the transfer of charge between the charge transfer circuit and a load in a timed, periodic manner; hence, charge transfer circuits are often conventionally referred to as “switched” circuits. These circuits generally accept or “sample” some form of input, sometimes referred to as a “reference” signal, and transfer a quantum of charge based on the sampled reference signal to or from the load only during particular respective time intervals. Such switched circuits may be contrasted with “continuous-time” circuits, which typically receive one or more continuous-time input signals over longer uninterrupted periods, and continuously provide one or more output signals based on the input signals.
One example of a charge transfer circuit that has been employed in sampled data systems is given by a switched capacitor circuit, as shown in FIG.
1
.
FIG. 1
shows that a conventional switched capacitor circuit
10
may include a capacitor
12
having a capacitance C, switches S
1
and S
2
, and a charge control circuit
16
having an input to receive a clock signal
18
. The clock signal
18
has a period
19
which defines successive timing intervals
21
and
23
, during which the charge control circuit
16
operates the switches S
1
and S
2
in a particular manner.
The switched capacitor circuit
10
shown in
FIG. 1
functions generally as follows. During a first time interval
21
defined by the period
19
of the clock signal
18
, the charge control circuit
16
operates the switch S
1
to connect circuit nodes
20
and
22
, and operates the switch S
2
to connect circuit nodes
24
and
26
, as shown by the dashed lines in FIG.
1
. Accordingly, during the first time interval
21
, the capacitor
12
is connected between a reference source
14
and a ground potential, and is charged, or “preset,” by a reference signal
15
output by the reference source
14
. The reference signal
15
may be, for example, a reference voltage V
ref
, in which case the capacitor
12
is preset to have a particular stored charge Q (in coulombs), given by Q=CV
ref
. Hence, this first time interval
21
is often referred to as a “preset” interval. The charge Q stored on the capacitor
12
may be viewed as representing a “sample” of the reference signal
15
, namely the voltage V
ref
, taken during the preset interval
21
.
During a second time interval
23
, also defined by the period
19
of the clock signal
18
and following the first time interval
21
, the charge control circuit
16
operates the switch S
1
to connect circuit nodes
28
and
22
, and operates the switch S
2
to connect circuit nodes
24
and
30
(opposite to the switch positions shown by the dashed lines in FIG.
1
). Accordingly, during the second time interval
23
, the capacitor
12
is disconnected from the reference source
14
and connected to a load
32
, whereupon the charge Q stored on the capacitor
12
is transferred between the capacitor and the load. Hence, this second time interval
23
is often referred to as a “transfer” interval, during which the “sample” of the reference voltage V
ref
in the form of the charge Q is transferred to the load
32
.
In the switched capacitor circuit of
FIG. 1
, the capacitor
12
may be positively or negatively charged by the reference signal
15
; in particular, depending on the relative polarities of the capacitor and the reference signal
15
, which may be, for example, a positive or negative voltage ±V
ref
, the capacitor may be charged during the preset interval
21
such that the capacitor may either transfer a charge Q to, or draw a charge Q from, the load
32
during the transfer interval.
Additionally, in the circuit of
FIG. 1
, the period
19
of the clock signal
18
is preferably chosen so that the preset interval
21
and the transfer interval
23
are long enough to allow the capacitor
12
to be fully charged to Q=CV
ref
, and discharged so as to fully transfer the charge Q to or from a load, during these intervals, respectively. If this were not the case, the charge Q stored on the capacitor
12
during the preset interval
21
likely would be less than CV
ref
, and hence would not represent an accurate sample of the reference signal
15
. Moreover, whatever charge Q was in fact stored on the capacitor
12
during the preset interval
21
likely would not be fully transferred to the load during the transfer interval
23
if the period
19
of the clock signal
18
was not sufficiently long, further exacerbating the inaccuracy of the transferred charge as a representation of the sampled reference signal
15
. This situation also can lead to an unpredictable transfer of charge to the load in successive periods of the clock signal, in which case the transferred charges may not consistently and accurately reflect the sampled voltage V
ref
of the reference signal
15
over longer time intervals. Such a dependence of the transferred charge on the period of the clock signal is generally referred to as “jitter sensitivity.”
However, as discussed above, if the period
19
of the clock signal
18
is sufficiently long, based on the capacitance C and the reference signal
15
(for example, the voltage V
ref
), the dynamics of the switched capacitor circuit
10
, such as the operation of the switches S
1
and S
2
, ideally have no effect on the transfer of the charge Q between the switched capacitor circuit
10
and the load
32
. Conventional switched capacitor charge transfer circuits generally are designed with this concept in mind, and thus are relatively insensitive to variations in the period of the clock signal, or “clock jitter.” However, other types of conventional charge transfer circuits, such as switched current source charge transfer circuits, are quite sensitive to clock jitter.
While some conventional charge transfer circuits suffer from a problem of clock jitter sensitivity, as discussed above, Applicant has identified that conventional charge transfer circuits generally suffer from other drawbacks that may impede the fabrication of monolithic integrated circuits including switched charge transfer circuits; in particular, such drawbacks may impede the fabrication of monolithic integrated circuits that mix switched charge transfer circuits with continuous-time circuits.
In view of the foregoing, charge transfer methods and apparatus that overcome various drawbacks specifically identified by the Applicant, as discussed in greater detail below, would offer several advantages to the electronics industry, particularly in the area of sampled data systems.
SUMMARY OF THE INVENTION
The present invention is directed to methods and apparatus for jitter and load insensitive charge transfer.
In one embodiment of the invention, a charge transfer circuit to transfer a quantity of charge to or from a load comprises a clock input to receive a clock signal having a period, wherein a portion of the period defines a transfer interval, and at least one reference input to receive at least one reference signal. In this embodiment, the quantity of charge transferred by the charge transfer circuit is based on the at least one reference signal. Additionally, the charge transfer circuit transfers the q

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