Metal working – Barrier layer or semiconductor device making
Reexamination Certificate
1997-12-09
2002-07-23
Graybill, David E. (Department: 2827)
Metal working
Barrier layer or semiconductor device making
C269S021000, C277S910000
Reexamination Certificate
active
06423102
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technique for conducting die-bonding and wire-bonding operations while supporting a circuit-bearing surface of a semiconductor integrated circuit chip in a die-bonding process as well as in a wire-bonding process for the semiconductor integrated circuit chip, and more specifically concerns a jig used for assembling semiconductor devices which is capable of reducing damages to the circuit-bearing surface of the semiconductor integrated circuit chip and a manufacturing method for semiconductor devices wherein such a jig is used.
BACKGROUND OF THE INVENTION
In general, semiconductor integrated circuit chips (hereinafter, referred to as “chips”) are produced as follows: First, a chip is die-bonded onto a die pad of a lead frame through Ag paste, and after the Ag paste has been cured, bonding pads, formed on the chip, are wire-bonded to inner leads of the lead frame by the use of bonding wire or other members. After having sealed these with sealing materials such as resins and ceramics, tie bars and side bars are cut off, and outer leads are bent into desired shapes; thus, the chip is completed.
In recent years, there have been increasing demands for high-density, thin ICs, and in order to meet these demands, there have been proposed ICs wherein chips are bonded on both the back and surface sides of a lead frame. As shown in FIG.
8
(
a
), in a die-bonding operation and a wire-bonding operation of such chips, the first chip
24
a
is die-bonded by a bonding collet
29
onto a die pad
23
a
on the first-surface side of a lead frame
22
that has been mounted on a support stage
25
, in the same manner as the normal process, and the Ag paste is cured.
Next, as shown in FIGS.
8
(
b
) through
8
(
d
), the chip
24
a
is clamped by a heater block
30
and a clamp plate
31
, and is fixed by applying a vacuum suction onto the back surface of the first-surface side die pad
23
a
through a suction hole
32
. Then, while applying heat, the bonding pads of the first chip
24
a
and the inner leads on the first-surface side of the lead frame
22
are wire-bonded to each other through bonding wires
26
.
Then, the lead frame
22
is turned over to be upside down, and as shown in FIG.
8
(
e
), the second IC chip
24
b
is die-bonded onto a die pad
23
b
on the second-surface side of the lead frame
22
that has been mounted on a support stage
45
by using a bonding collet
29
. The support stage
45
has a groove section
28
a
that is provided for preventing the first chip
24
a
that has been subjected to the die-bonding and wire-bonding from contacting the bonding wires
26
, an inner section
45
a
for supporting the surface of the first chip
24
a
, and an outer section
45
b
for supporting the lead frame
22
.
As shown in FIGS.
8
(
f
),
8
(
g
) and
8
(
h
), after the Ag paste has been cured, this is clamped by a heater block
50
and the clamp plate
31
. The heater block
50
has a groove section
28
b
that is provided for preventing the first chip
24
a
that has been subjected to the die-bonding and wire-bonding from contacting the bonding wires
26
, an inner section
50
a
for supporting the surface of the first chip
24
a
, a suction hole
52
that is formed in the inner section
50
a
, and an outer section
50
b
for supporting the lead frame
22
. Then, while applying a vacuum suction onto the surface of the first chip
24
a
through the suction hole
52
so as to fix the chip therein, as well an applying heat, the bonding pads on the surface of the second chip
24
b
and the inner leads of the lead frame
22
are wire-bonded to each other through bonding wires
26
.
After having sealed the first chip
24
a
and the second chip
24
b
with sealing materials such as resins and ceramics at the same time, tie bars and side bars are cut off, and outer leads are bent into desired shapes; thus, the product is completed.
Moreover, another method has been proposed by Japanese Patent Publication No. 121462/1993 (Tokukaihei 5-121462).
After the first chip has been die-bonded onto a die pad on the first-surface side of a lead frame and the Ag paste has been cured, inner leads on the first-surface side and the bonding pads of the first chip are wire-bonded to each other through bonding wires, and only the inner leads on the first-surface side and the first chip are subjected to a resin-sealing process beforehand.
Next, the lead frame is turned over to be upside down, and after the second chip has been die-bonded onto the second-surface side of the lead frame and the Ag paste has been cured, inner leads on the second-surface side and the bonding pads of the second chip are wire-bonded to each other through bonding wires, and then the inner leads on the second-surface side of the lead frame and the second chip are subjected to a resin-sealing process.
In these methods, however, when the die-bonding operation and the wire-bonding operation are carried out on the second chip
24
b
of the lead frame
22
, the circuit-bearing surface of the first chip
24
a
of the lead frame
22
needs to be contacted and supported by the inner section
45
a
of the support stage
45
and the inner section
50
a
of the heater block
50
; this causes a pressure onto the circuit-bearing surface, resulting in the following problems.
Here, FIGS.
9
(
a
) and
9
(
b
), which explain a principle as to how cracks develop in a passivation film
33
during the forming process by the die-bonding and wire-bonding jig used in the conventional technique, are enlarged drawings, each of which shows a contacting and supporting section between the circuit-bearing surface of the first chip
24
a
of the lead frame
22
and the surface of the inner section
45
a
of the support stage
45
or the surface of the inner section
50
a
of the heater block
50
.
As shown in FIG.
9
(
a
), the passivation film
33
having a film-thickness of approximately 1 &mgr;m is coated on the circuit-bearing surface of the first chip
24
a
, and serves an a final protective film. Here, it is actually inevitable to have minute protrusions and recessions on the surface of the inner section
45
a
of the support stage
45
(hereinafter, referred to as “the first supporting face”) as well as on the surface of the inner section
50
a
of the heater block
50
(hereinafter, referred to as “the second supporting face”) due to their machining processes, and the biggest protrusion
35
, located thereon, partially comes into contact with the passivation film
33
. As a result, a die-bonding load as well as a wire-bonding load is locally applied onto the passivation film
33
, and this tends to cause a crack
36
due to concentration of stress.
Moreover, as shown in FIG.
9
(
b
), if there is foreign matter, such as silicone fragments, having a comparatively high hardness and having sharp shapes between the passivation film
33
and the first supporting face or the second supporting face, the biggest foreign matter
34
, located thereon, partially comes into contact with the passivation film
33
. As a result, a die-bonding load as well as a wire-bonding load is locally applied onto the passivation film
33
, and this tends to cause a crack
36
due to concentration of stress.
Here, the concentration of stress, which forms a main cause of the crack
36
, is caused and developed mainly due to the fact that the first supporting face and the second supporting face are made of a rigid material such as a metallic material of iron group.
Cracks caused in the passivation film tend to reduce the humidity resistance of the chip, and those chips containing cracks tend to be extracted as defective ones during electrical-characteristic tests and reliability tests that are carried out after they have been sealed with resin; this results in a reduction in the final yield of the chips.
Furthers in the method of the above-mentioned Japanese Patent Publication No. 121462/1993 (Tokukaihei 5-121462), those processes, such as die-bonding, Ag-paste curing, wire-bonding and resin-sealing processes, need to be ca
Fukunaga Satoru
Nakanishi Hiroyuki
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