JFET with drain and/or source modification implant

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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Details

C257S272000, C257SE29314, C438S186000, C438S194000

Reexamination Certificate

active

07411231

ABSTRACT:
The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

REFERENCES:
patent: 4176368 (1979-11-01), Compton
patent: 4816880 (1989-03-01), Muro
patent: 5008719 (1991-04-01), Schrantz
patent: 5907168 (1999-05-01), Childs
patent: 61073380 (1986-04-01), None
patent: 2000174035 (2000-06-01), None
patent: WO 2007/075759 (2007-07-01), None

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