JFET Differential amplifier stage with method for controlling in

Amplifiers – With semiconductor amplifying device – Including differential amplifier

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330277, 330311, H03F 316, H03F 345

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045381151

ABSTRACT:
A JFET differential amplifier stage in which the gate-drain voltage of each JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias currents. The JFETs are supplied with currents which force their gate-source voltages to at least 0.5 V.sub.p. A second pair of JFETs are cascoded with the first pair and also develop gate-source voltages of at least 0.5 V.sub.p. The gate-source terminals of the second pair are connected in a loop with the source-drain terminals of the first pair, thereby forcing the gate-drain voltages of the first pair to at least V.sub.p, the minimum voltage necessary to hold the first pair in a desired saturated state. A third pair of JFETs is connected to buffer the first pair from capacitances developed at the gates of the second pair without effecting the AC operation of the circuit.

REFERENCES:
Wyland, D. C., "FET Cascode Technique Optimizes Differential Amplifier Performance", Electronics, 1-18-71, pp. 81-84.
Burr-Brown OPA-111 Catalogue Sheet, 1984, OPA-100 Catalogue Sheet, 1983.
Steve Millaway, "Monolithic OP Amp Hits Trio of Lows", Electronic Design, Feb. 9, 1984, pp. 97-101.
Harris Corporation, HA-5180/5180A Catalogue Sheet, 1982.
Precision Monolithics, Inc., OP-215 Catalogue Sheet, 1983.

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