JFET base junction transistor clamp

Details JFET base junction transistor clamp JFET base junction transistor clamp

1976-10-22

1978-10-03

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307280, 307300, 307304, H03K 508

Patent

active

041186400

ABSTRACT:
A base junction transistor inverter circuit will be driven into the saturation region if the drive current is large enough. In such circumstances, the collector voltage can go below the base voltage and approaches the emitter voltage. A circuit is provided to keep the transistor out of saturation and is comprised of a p-channel field effect transistor (JFET) connected between the base and collector of the junction transistor. The JFET is connected such that when the drive current increases and the junction transistor approaches saturation, the drive current is diverted through the JFET and into the substrate. The same clamp can be implemented by using a pnp junction transistor in combination with an n-channel JFET.

REFERENCES:
patent: 3160765 (1964-12-01), Krossa
patent: 3482111 (1969-12-01), Gunderson et al.
patent: 3534281 (1970-10-01), Hillhouse
patent: 3621284 (1971-11-01), Cluett et al.
patent: 3657577 (1972-04-01), Wakai et al.
patent: 3665345 (1972-05-01), Dolby
patent: 3763382 (1973-10-01), Horichi et al.
patent: 3845405 (1974-10-01), Leidrich
patent: 4013975 (1977-03-01), Kataoka et al.
Hong et al., "Nonsaturating Logic Circuit", IBM Tech. Discl. Bull,; vol. 14, No. 5, pp. 1592, 10/1971.

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