JFET active load input stage

Details JFET active load input stage JFET active load input stage

1984-05-31

1987-08-18

Shaw, Clifford C.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

330258, H03F 368

Patent

active

046879846

ABSTRACT:
An active load circuit for operational amplifiers and the like is described which provides an improved common mode rejection ratio and common mode voltage range, and alleviates transistor saturation and cut off problems during maximum slew rates. Drive currents from the operational amplifier or other circuit are transmitted directly through respective load resistors, thereby reducing voltage offsets which degrade common mode rejection ratio. At the same time the absolute voltage levels at the operational amplifier or like circuit are reduced, thereby increasing the common mode voltage range. A pair of active load transistors are supplied with current from current sources independent of the amplifier transistors, and deliver their respective currents to the same resistors which receive the amplifier currents. An output is taken from one of the load transistors without connecting to either of the amplifier transistors.

REFERENCES:
patent: 3851270 (1974-11-01), Vosteen
patent: 4121169 (1978-10-01), Iwamatsu
patent: 4553107 (1985-11-01), Ogawa

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