Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2001-01-23
2003-11-25
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S077000, C257S135000, C257S136000, C257S196000, C257S197000, C438S137000, C438S138000, C438S931000, C438S173000, C438S192000
Reexamination Certificate
active
06653666
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an FET semiconductor configuration and, in particular, a vertical J-FET semiconductor configuration having a first semiconductor region, which includes a first contact with a highly doped contact layer serving as a source that is between two second contacts serving as a gate on its first surface.
In power switching technology, fast switching elements are sought which have the lowest possible static and dynamic losses and which can be driven with a low outlay. Power components of this type are used e.g. as DC switches in converters for variable-speed drives or as AC voltage switches (1- or 3-phase) of motor branch circuits. The low power loss permits compact devices with high efficiency.
For reverse voltages of 600 V, 1200 V, 1800 V . . . , nowadays mainly silicon IGBTs are used which have a threshold voltage in the forward direction.
The disadvantage in this prior art, however, is that power derating occurs in highly dynamic motor controllers with bipolar IGBTs, on account of the switching losses caused by the bipolar stored charge.
Although the switching losses are drastically reduced by using fast unipolar power MOSFETS made of silicon, the on-state losses or the on resistivity in the reverse voltage ranges mentioned is considerable, and the chip areas have to be chosen to be large. This results in higher costs and is therefore often the decisive factor in favor of the IGBT.
The following have been proposed as improved FETs of this type: a MOSFET using Si technology (proposed by Tihany in DE 43 09 764 C2) and a vertical J-FET which, in particular, can be fabricated using SiC technology (proposed by Mitlehner et al. in WO 97/23911 A1). The J-FET according to this prior art has a second semiconductor region within a first semiconductor region below a contact. The first and second semiconductor regions are of opposite conductivity types. The second semiconductor region serves to shield the source from the drain and extends beyond the contact in a projection onto the surface of the semiconductor, so that at least one channel region is formed in the first semiconductor region. The channel region is bounded toward the bottom by the depletion zone of the pn junction formed between the first semiconductor region and the second semiconductor region and transports an electric current from or to the contact in an on state.
However, the second semiconductor regions within the first semiconductor regions are complicated to fabricate. In particular, it is difficult to fabricate the components in SiC, inter alia, because of the thermal properties thereof: the implantation must be carried out very accurately over the entire desired area of the second semiconductor region, since it is no longer possible subsequently to adapt the expansion of the second semiconductor region through diffusion in SiC. On the other hand, the fabrication of components with a high blocking capability in SiC is of interest since SiC has, compared with Si, a very high breakdown field strength and very good on-state properties.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a switching element which overcomes the above-mentioned disadvantageous of the prior art switching elements of this general type, and specifically, to provide a low-loss, fast and short-circuit-proof switching element which is simple and thus cost-effective to fabricate. In this regard, reverse voltages are typically in the region of 600 V, 1200 V, 1800 V.
With the foregoing and other objects in view there is provided, in accordance with the invention a vertical J-FET semiconductor configuration that includes: a semiconductor region of a first conductivity type defining a first semiconductor region having a first surface; and a first contact with a highly doped contact layer serving as a source. The first contact is disposed on the first surface. Two second contacts serve as a gate. The first contact is disposed between the two second contacts. Three second semiconductor regions are of a second conductivity type that is opposite the first conductivity type. A first one of the second semiconductor regions is connected to the first contact. A second one of the second semiconductor regions is connected to one of the two second contacts. A third one of the second semiconductor regions is connected to another one of the two second contacts. The second one of the second semiconductor regions and the third one of the second semiconductor regions extend in the first semiconductor region below the first one of the second semiconductor regions. The three second semiconductor regions at least partially overlap in a projection onto a horizontal plane. At least one channel region is formed in the first semiconductor region and between the three second semiconductor regions.
According to the invention, in contrast to the prior art, at least some of the second semiconductor regions are not produced as “islands”, over which a further epitaxial layer is then configured. Rather all of the second semiconductor regions are produced as areas at the surface of the component. The design of the semiconductor element according to the invention is very much simpler in terms of production engineering and that enables the component to be fabricated in a particularly cost-effective manner from materials which are difficult to handle, such as SiC.
The J-FET semiconductor configuration according to the invention is characterized in that the three contacts are each connected to a second semiconductor region. The first and second semiconductor regions are of opposite conductivity types. The second semiconductor regions that are connected to the second contacts extend in the first semiconductor region below the second semiconductor region that is connected to the first contact, with the result that the three second semiconductor regions at least partially overlap in a projection onto a horizontal plane and at least one channel region is formed between the three second semiconductor regions in the first semiconductor region.
In accordance with an added feature of the invention, the first contact has at least one cutout, so that there is an electrical contact between the first contact and the second semiconductor region under the second contact. This avoids floating of the second semiconductor region.
In accordance with an additional feature of the invention, dielectric passivation of the component is provided. The dielectric passivation layer is provided in each case between the first contact and the second contact on the surface of the first semiconductor region and is formed by either an oxide layer or a semiconductor layer which is doped in such a way that it has an opposite conductivity type to that of the first semiconductor region. Greater stability is achieved as a result of this.
One advantage of the invention is that the power loss of the J-FET semiconductor configuration according to the invention is approximately one order of magnitude below that of conventional Si-IGBTs in this power range. Moreover, the linear expansion of the vertical drift region W
ch vert
can be chosen to be large since the second semiconductor region under the highly doped contact layer of the first contact (=source) provides for the necessary shielding without adversely affecting the reverse voltage.
A further advantage of the invention is that the output capacitance is low since a large-area second semiconductor region is attached to the highly doped contact layer of the first contact (=source). This also results in a further decrease in the switching losses since the charge reversal of the second contact (=gate) is reduced.
Furthermore, the static losses of the J-FET according to the invention are particularly low since the drift zone is utilized optimally.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a J-FET semiconductor confi
Mitlehner Heinz
Weinert Ulrich
Cao Phat X.
Greenberg Laurence A.
Le Thao X.
Locher Ralph E.
SiCED Electronics Development GmbH & Co. KG
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