Iterative high radix divider decoding the upper bits of a diviso

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G06F 752

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052068277

ABSTRACT:
A divider unit is provided for a high-radix division using a partial remainder. A quotient digit selecting device selects one from all quotient digits obtainable under an applied radix based on the signs and the upper digit values of the divisor and the partial remainder represented in the two's complement representation or, alternatively, on the upper digit values of the divisor and the partial remainder represented in the redundant binary representation. A number of divisor's multiple generating devices each generate at least one of 0 and a value obtained by multiplying the divisor with 2.sup.j (j=integer). At least one adding and subtracting device provides at least three inputs to generate a first product corresponding to any desired multiple of the divisor by adding or subtracting the outputs from the multiple generating devices and to generate another partial remainder by adding or subtracting the first product with a second product corresponding to a value obtained by multiplying the partial remainder by the radix.

REFERENCES:
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patent: 4722069 (1988-01-01), Ikeda et al.
Jackson et al., "Binary Multiplication and Division Utilizing a Three-Input Adder" IBM Tech. Disclosure Bulletin vol. 15 No. 7 Dec. 1992 pp. 2263-2268.
A partial Japanese translation of Kai Hawng, "Computer Arithmetic/Principles, Architecture, and Design", John Wiley & Sons, 1979 (Ch. 7, sec. 9-11).
D. E. Atkins, "Higher Radix Division Using Estimates of the Divisor and Partial Remainders", IEEE Trans. Computers, vol. C-17, No. 10, pp. 925-934, Oct. 1986.
D. E. Atkins, "Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods" IEEE Trans. Computers, vol. C-19, No. 8, pp. 720-732.

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