Iterative division apparatus, system and method forming plural q

Details Iterative division apparatus, system and method forming plural q Iterative division apparatus, system and method forming plural q

1994-10-17

1995-08-15

Mai, Tan V.

Boots, shoes, and leggings

364761, G06F 752

Patent

active

054425816

ABSTRACT:
An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2.sup.M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2.sup.M -1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.

REFERENCES:
patent: 3145296 (1964-08-01), Sweeney
patent: 3234366 (1966-02-01), Davis et al.
patent: 3684879 (1972-08-01), Koehler
patent: 3852581 (1974-12-01), Reynard et al.
patent: 4320464 (1982-03-01), Desmonds
patent: 4384341 (1983-05-01), Tague et al.
patent: 4665500 (1987-05-01), Poland
patent: 4821225 (1989-04-01), Ando et al.
patent: 4872131 (1989-10-01), Kubota et al.
patent: 4891780 (1990-01-01), Miyoshi
patent: 4989173 (1991-01-01), Kaneda
patent: 5012439 (1991-04-01), Nash et al.
patent: 5014233 (1991-05-01), Kihaya et al.
patent: 5016210 (1991-05-01), Sprague et al.
patent: 5105378 (1992-04-01), Mori
patent: 5197140 (1993-03-01), Balmer
patent: 5206828 (1993-04-01), Shah et al.
patent: 5212777 (1993-05-01), Gove et al.
patent: 5214599 (1993-05-01), Magerman
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5239654 (1993-08-01), Simmons et al.
patent: 5272660 (1993-12-01), Rossbach
Microprocessor Report, Slater, Michael, "IIT Ships Programmable Video Processor", vol. 5, No. 20, Oct. 30, 1991, pp. 1, 6-7, 13.
Chris Rowen, Mark Johnson and Paul Ries; Journal Article Entitled: The MIPS R3010 Floating-Point Coprocessor; IEEE Micro; Jun. 1988, pp. 53-62.
D. Aktins, Higher-Radix Division Using Estimates of the Divisor and Partial Remainders; IEEE Trans. Computers; 1968; pp. 925-934.
G. Taylor; Radix 16 SRT Dividers With Overlapped Quotient Selection Stages; Proc. Seventh IEEE Symp. Computer Arithmetic; Jun. 1985; pp. 64-71.

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