Iterative arithmetic processor

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364736, G06F 700, G06F 738

Patent

active

055703097

ABSTRACT:
A mantissa X.sub.Mk, which satisfies 1.ltoreq.X.sub.Mk <2, is fed to a mantissa process section in order that the iterative multiplication operation of normalized floating-point numbers X.sub.k (k=0, . . . , m), written P=X.sub.0 .times.X.sub.1 .times.X.sub.2 .times.0 . . . .times.X.sub.m, is performed. In the mantissa process section, a product represented in RB (redundant binary) number representation is stored in a register, and such a product is fed back to a multiplier without being converted into a binary number. A shifter for one-place right-shift is provided between the multiplier and the register. A converter sequentially converts each RB number stored in the register into a binary number and provides to the shifter a shift-amount signal S.sub.1 whose value varies with the result of such RB-to-binary number conversion. If a digit that is positioned upward two places from the binary point of a binary number obtained by the conversion is 0, then the value of S.sub.1 is set to 0. If such a digit is 1, then the value of S.sub.1 is set to 1.

REFERENCES:
patent: 4935892 (1990-06-01), Nishiyama
patent: 4985861 (1991-01-01), Yamashina et al.
patent: 5031136 (1991-07-01), Nishiyama et al.
patent: 5040138 (1991-08-01), Maher, III
patent: 5153847 (1992-10-01), Takagi et al.
patent: 5251166 (1993-10-01), Ishida

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